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Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0

11-6

Freescale Semiconductor

Triple Timer Module (TEC, TEC_1)

11.4.2

Reserved Modes

Modes 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15 are reserved.

11.4.3

Special Cases

The following special cases apply during wait and stop state.

•

Timer behavior during wait—Timer clocks are active during the execution of the WAIT instruction
and timer activity is undisturbed. If a timer interrupt is generated, the DSP56725 leaves the wait
state and services the interrupt.

•

Timer behavior during stop—During execution of the STOP instruction, the timer clocks are
disabled, timer activity stops, and the TIO signals are disconnected. Any external changes that
happen to the TIO signals are ignored when the corresponding DSP Core is in stop state. To ensure
correct operation, disable the timers before the corresponding DSP Core is placed into stop state.

11.4.4

DMA Trigger

Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a timer
event. The timer issues a DMA trigger on every event in all modes of operation. To ensure that all DMA
triggers are serviced, provide for the preceding DMA trigger to be serviced before the DMA channel
receives the next trigger.

Figure 11-4. Timer Mode (TRM = 0)

Mode 0 (Internal clock, no timer output): TRM = 0

N = write preload

M = write compare

TE

Clock

(CLK/2 or prescale CLK)

TLR

TCPR

TCF (Compare Interrupt if TCIE = 1)

Counter (TCR)

first event

last event

M

N

TOF (Overflow Interrupt if TCIE = 1)

0

N

N + 1

M

0

1

M + 1

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Summary of Contents for Symphony DSP56724

Page 1: ...Document Number DSP56724RM Rev 0 6 2008 Symphony DSP56724 DSP56725 Multi Core Audio Processors Reference Manual ...

Page 2: ...articular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and act...

Page 3: ... 7 1 4 10 External Memory Controller EMC 1 7 1 4 11 Clock Generation Module CGM 1 7 1 4 12 Shared Memory 1 8 1 4 13 Inter Core Communication ICC 1 8 1 4 14 Shared Bus Arbiters 1 8 1 4 15 Chip Configuration Module 1 8 1 4 16 JTAG Controller 1 9 Chapter 2 Signal Descriptions 2 1 Signal Groupings 2 1 2 2 Signals in Each Functional Group 2 5 2 2 1 Power 2 5 2 2 2 Ground 2 5 2 2 3 SCAN 2 6 2 2 4 Clock ...

Page 4: ...ernal Buses 4 5 4 3 5 OnCE Module 4 6 Chapter 5 Core Configuration 5 1 Introduction 5 1 5 2 Operating Mode Register OMR 5 1 5 3 Status Register SR 5 3 5 4 DSP Cores Operating Modes 5 6 5 5 Interrupt Priority Registers 5 9 5 6 DMA Request Sources 5 19 5 7 Chip ID Register 5 20 Chapter 6 Core Integration Module CIM CIM_1 6 1 Overview 6 1 6 1 1 Memory Map 6 2 6 1 2 Register Summary 6 2 6 2 Register D...

Page 5: ... 9 8 2 6 Timer Event Counter Signals 8 10 Chapter 9 Enhanced Serial Audio Interface ESAI ESAI_1 ESAI_2 ESAI_3 9 1 ESAI Data and Control Pins 9 3 9 1 1 Serial Transmit 0 Data Pin SDO0 9 3 9 1 2 Serial Transmit 1 Data Pin SDO1 9 3 9 1 3 Serial Transmit 2 Receive 3 Data Pin SDO2 SDI3 9 3 9 1 4 Serial Transmit 3 Receive 2 Data Pin SDO3 SDI2 9 4 9 1 5 Serial Transmit 4 Receive 1 Data Pin SDO4 SDI1 9 4 ...

Page 6: ...alization Examples 9 50 9 5 1 Initializing the ESAI Using Individual Reset 9 50 9 5 2 Initializing Only the ESAI Transmitter Section 9 50 9 5 3 Initializing Only the ESAI Receiver Section 9 51 9 6 ESAI ESAI_2 and ESAI_1 ESAI_3 Pin Switch 9 51 9 7 Internal Clock Connections Between ESAI and ESAI_1 ESAI_2 and ESAI_3 9 52 Chapter 10 Serial Host Interface SHI SHI_1 10 1 Introduction 10 1 10 2 Serial H...

Page 7: ... Operating Mode 11 4 11 4 1 Timer GPIO Mode 0 11 5 11 4 2 Reserved Modes 11 6 11 4 3 Special Cases 11 6 11 4 4 DMA Trigger 11 6 11 5 Triple Timer Module Programming Model 11 7 11 5 1 Prescaler Counter 11 7 11 5 2 Timer Prescaler Load Register TPLR 11 8 11 5 3 Timer Prescaler Count Register TPCR 11 9 11 5 4 Timer Control Status Register TCSR 11 9 11 5 5 Timer Load Register TLR 11 12 11 5 6 Timer Co...

Page 8: ... Core Non Maskable Interrupts 13 14 13 3 3 Polling 13 15 13 3 4 Error Interrupts 13 15 13 3 5 Reset 13 16 Chapter 14 Shared Bus Arbiter 14 1 Introduction 14 1 14 1 1 Overview 14 1 14 1 2 Features 14 1 14 2 Memory Map and Register Definition 14 2 14 3 Functional Description 14 2 14 3 1 Shared Bus Arbitration 14 2 Chapter 15 Shared Memory Shared Memory 15 1 Overview 15 1 15 2 Block Diagram 15 1 Chap...

Page 9: ...egisters 18 9 18 2 6 S PDIF Transmission Registers 18 11 18 2 7 S PDIF FreqMeas Register SRFM 18 14 18 2 8 SPDIFTxClk Register STC 18 14 18 3 S PDIF Receiver 18 15 18 3 1 Audio Data Reception 18 15 18 3 2 Channel Status Reception 18 18 18 3 3 User Bit Reception 18 18 18 3 4 Validity Flag Reception 18 20 18 3 5 S PDIF Receiver Interrupt Exception Definition 18 21 18 3 6 Standards Compliance 18 22 1...

Page 10: ...20 3 3 Soft Reset 20 16 20 3 4 Reset 20 17 20 3 5 ESAI Pin Switch and Internal Clock Connections 20 17 Chapter 21 External Memory Controller EMC 21 1 Introduction 21 1 21 1 1 Features 21 2 21 2 External Signal Descriptions 21 3 21 2 1 Detailed Signal Descriptions 21 4 21 3 Memory Map and Register Definition 21 7 21 3 1 Memory Map 21 7 21 3 2 Register Descriptions 21 9 21 4 Functional Description 2...

Page 11: ...amplifiers and professional audio equipment Revision History The following table summarizes revisions to this document Audience The Symphony DSP56724 DSP56725 Multi Core Audio Processors Reference Manual provides to the design engineer the necessary data to successfully integrate the processors into a wide variety of applications The intended audience for this document includes system architects s...

Page 12: ...its means to establish logic level one To clear a bit or bits means to establish logic level zero A signal is an electronic construct whose state conveys or changes in state convey information A pin is an external physical connection The same pin can be used to connect a number of signals Asserted means that a discrete signal is in active logic state Active low signals change from logic level one ...

Page 13: ...ck each core includes Highly parallel instruction set Hardware debugging support JTAG TAP OnCETM module Eight channel DMA controller Wait and Stop low power standby modes Configurable and flexible arbitration method for the shared peripherals and shared memory blocks Powerful audio data communication ability Four Enhanced Serial Audio Interface ESAI modules to transmit and receive audio data Two E...

Page 14: ...sible to both cores to support different sample rate audio data transmission reception Three data sampling rate convert pairs can be supported at the same time Different pairs can be used by different cores at the same time Inter Core Communication ICC module 32K shared memory between the two DSP56300 cores Supports a flexible arbitration system which allows multiple methods of arbitration Non mas...

Page 15: ...hared Bus 1 Memory Bus ESAI_1 SHI TEC PIC DMA WDT CIM ESAI_2 ESAI_3 SHI_1 TEC_1 PIC_1 DMA_1 WDT_1 CIM_1 Internal Memory 1 GPIO A G Chip Configuration Shared Bus Arbiter 7 Shared Mem0 8K Core 0 Core 1 Memory Bus Shared Mem7 8K GPIO_1 GPIO Inter Core Comm ICC CGM ASRC Memory Bus Dedicated Peripheral Bus Shared Bus Arbiter 0 Shared Bus Arbiter 9 Shared Bus Arbiter 8 EMC Burst Buffer Shared Peripheral...

Page 16: ... various configurations of memory and peripheral modules The peripherals are interfaced to the DSP56300 family core through a peripheral interface bus that provides a common interface to many different peripherals Sophisticated Debugging Freescale s On Chip Emulation OnCE technology allows simple inexpensive and speed independent access to the internal registers for debugging With the OnCE module ...

Page 17: ...ip configuration module JTAG controller 1 4 1 Direct Memory Access Controller DMA DMA_1 The DMA controller enables data transfers without any interactions with the DSP cores During DMA accesses it supports any combination of source and destination between internal memory internal peripheral I O and external memory DMA features include Eight DMA channels supporting internal and external accesses On...

Page 18: ... overhead the SHI supports single double and triple byte data transfers The SHI has a 10 word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt reducing the overhead for data reception 1 4 5 Triple Timers TEC TEC_1 Each Triple Timer is composed of a common 21 bit prescaler and three independent and identical general purpose 24 bit timer event counters with ea...

Page 19: ...nnels of about 120 dB THD N The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates The ASRC supports up to three sampling rate pairs Although there is only one ASRC in the DSP56724 DSP56725 device shared by the two DSP cores the three sample rate pairs can be used by both DSP cores at the same time The ASRC is hard coded and implemented as a co p...

Page 20: ...ferent 8K x 24 SRAM blocks simultaneously 1 4 13 Inter Core Communication ICC Using the inter core communication module each DSP core can issue a maskable interrupt or non maskable interrupt to the other core and each core has its own write data register which passes data to the other core when the interrupt is generated There are also poll data registers for inter core data exchange in the ICC Th...

Page 21: ...conductor 1 9 EMC PLL control and status 1 4 16 JTAG Controller In the DSP56724 DSP56725 devices two separate DSP cores are supported each with their own OnCE and JTAG TAP controller The two JTAG TAPs are daisy chained and appear to be two separate single core devices to the outside world ...

Page 22: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 1 10 Freescale Semiconductor Introduction ...

Page 23: ...0 SDO1 FST FSR SCKT SCKR HCKT HCKR1 1 Clock and Frame Sync signals can be shared with ESAI No SDO0 SDO1 FST FSR SCKT SCKR HCKT HCKR1 ESAI_2 No SDO0 SDO1 FST FSR SCKT SCKR HCKT HCKR2 2 Clock and Frame Sync signals can be shared with ESAI_3 No SDO0 SDO1 FST FSR SCKT SCKR HCKT HCKR3 ESAI_3 No SDO0 SDO1 No SDO0 SDO1 HCKR Serial Host Interface SHI All All SHI_1 Only SS others muxed with SHI Only SS oth...

Page 24: ...6 10 9 Table 2 16 TEC_1 0 0 WDT_1 No GPIO Function 0 0 Pins of Shared Peripherals SPDIF Port G8 2 0 Table 2 19 EMC9 Port A7 48 0 Table 2 18 GPIO PORT G and Mode Pins Port G8 2 0 Table 2 20 JTAG OnCE Portfor the two DSP Cores 4 4 Table 2 21 Note 1 Port H signals are the GPIO port signals that are multiplexed with the SHI HREQ signal 2 Port C signals are the GPIO port signals that are multiplexed wi...

Page 25: ..._1 27 SDO5_1 SDI0_1 28 FSR 29 SCKR 30 HCKR 31 SCKT 32 IO_VDD 33 IO_GND 34 CORE_VDD 35 CORE_GND 36 FST 37 HCKT 38 SDO2 SDI3 39 SDO3 SDI2 40 SDO2_3 SDI3_3 1 SDO3_3 SDI2_3 2 SDO4_3 SDI1_3 3 SDO5_3 SDI0_3 4 IO_VDD 5 IO_GND 6 CORE_VDD 7 CORE_GND 8 SPDIFIN1 SDO2_2 SDI3_2 9 SPDIFOUT1 SDO3_2 SDI2_210 SDO4_2 SDI1_2 11 SDO5_2 SDI0_2 12 FSR_3 13 SCKR_3 14 SCKT_3 15 GND 16 GND 17 GND 18 GND 19 GND 20 80 SCAN ...

Page 26: ...GND 59 CORE_VDD 60 CORE_GND 61 LAD8 62 LAD7 63 LAD6 64 LAD5 65 LAD4 66 LAD3 67 LAD2 68 LAD1 69 LAD0 70 IO_GND 71 IO_VDD 72 CORE_VDD 1 CORE_GND 2 LALE 3 LCS0 4 LCS1 5 LCS2 6 LCS3 7 LCS4 8 LCS5 9 LCS6 10 LCS7 11 IO_VDD 12 IO_GND 13 CORE_VDD 14 CORE_GND 15 LWE 16 LOE 17 LGPL5 18 LSDA10 19 LCKE 20 LCLK 21 LBCTL 22 LSDWE 23 LSDCAS 24 LGTA 25 LA0 26 LA1 27 LA2 28 IO_VDD 29 IO_GND 30 PLLP1_GND 31 PLLP1_V...

Page 27: ...ance path to the 3 3 VDD power rail This is an isolated power for the SHI SHI_1 ESAI ESAI_1 ESAI_2 ESAI_3 Timer I O and other IO signals The user must provide adequate external decoupling capacitors Table 2 4 Ground Pins Ground Name Description PLLA_GND PLLP_GND PLLA1_GND PLLP1_GND PLL Ground The PLL ground should be provided with an extremely low impedance path to ground The user must provide ade...

Page 28: ...rted the state of the PLOCK pin is latched into the Core 0 MDC of Core 0 s OMR After RESET is de asserted PLOCK is output 0 and goes high when the internal PLL is locked MODC0 Input MODC0 MODA0 MODB0 MODC0 and MODD0 levels select one of 16 initial chip operating modes of DSP Core 0 and are latched into the DSP Core 0 s OMR when the RESET signal is de asserted PG0 Input Output or Disconnected GPIO ...

Page 29: ...equest A MODA0 IRQA is an active low Schmitt trigger input internally synchronized to the DSP clock MODA0 IRQA selects the initial Core 0 operating mode during hardware reset and becomes a two core shared level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing This pin can also be programmed as GPIO MODA0 MODB0 MODC0 and MODD0 levels select ...

Page 30: ...nnected GPIO Port G7 When the MODA1 IRQC is configured as GPIO this signal is individually programmable as input output or internally disconnected and this signal can be controlled by either of the two cores Uses an internal pull up resistor MODB1 IRQD Input MODB1 Input Mode Select B1 External Interrupt Request D MODB1 IRQD is an active low Schmitt trigger input internally synchronized to the DSP ...

Page 31: ... NMI1 Signal Name Type StateDuring Reset Description NMI1 Input MODC1 Input Nonmaskable interrupt for DSP Core 1 After RESET deassertion and during normal instruction processing the NMI1 Schmitt trigger input is a negative edge triggered nonmaskable interrupt request for DSP Core 1 and is internally synchronized to the internal system clock MODC1 Input Operating modes MODA1 MODB1 MODC1 and MODD1 l...

Page 32: ...us there is no need for an external pull up in this state This pin is shared by SHI and SHI_1 in DSP56725 80 pin and DSP56724 144 pin packages Uses an internal pull up resistor MISO Input or Output Tri stated SPI Master In Slave Out When the SPI is configured as a master MISO is the master data input line The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving se...

Page 33: ...6725 80 pin and DSP56724 144 pin packages Uses an internal pull up resistor SS Input Tri stated SPI Slave Select When configured for SPI Slave mode SS is used to enable the SPI slave for transfer and is an active low Schmitt trigger input When configured for SPI master mode SS should be kept de asserted pulled high If SS is asserted while configured in SPI master mode a bus error condition is flag...

Page 34: ... an external pull up in this state This pin is shared by SHI and SHI_1 in DSP56725 80 pin and DSP56724 144 pin packages Uses an internal pull up resistor Table 2 12 Serial Host Interface Signals SHI_1 Signal Name Signal Type State during Reset Description SS_1 Input Tri stated SHI_1 s SPI Slave Select When configured for SPI_1 Slave mode SS_1 is used to enable the SPI_1 slave for transfer and is a...

Page 35: ...or Disconnected GPIO Port C2 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected SRCK Output S PDIF Receive Clock This Pin can be used as S PDIF receive clock output this clock is generated by the internal S PDIF s DPLL controlled by the ERC0 bits in Pin MUX Control Register of the Chip Configuration Module The default state after...

Page 36: ...n the IF1 bit in the SAISR register synchronized by the frame sync in normal mode or by the slot in network mode PC1 Input Output or Disconnected GPIO Port C1 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Uses an internal pull down resistor FST Input or Output GPIO Disconnec...

Page 37: ...et is GPIO disconnected Uses an internal pull down resistor SCKT Input or Output GPIO Disconnected ESAI s Transmitter Serial Clock SCKT provides the serial bit rate clock for the ESAI SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode or by all enabled transmitters in asynchronous mode PC3 Input Output or Disconnected GPIO Port C3 When the ESAI is co...

Page 38: ... shift register SDI2 Input ESAI s Serial Data Input 2 When programmed as a receiver SDI2 is used to receive serial data into the RX2 serial receive shift register PC8 Input Output or Disconnected GPIO Port C8 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Uses an internal pul...

Page 39: ...rammed as a transmitter SDO4_1 is used to transmit data from the TX4 serial transmit shift register SDI1 Input ESAI_1 s Serial Data Input 1 When programmed as a receiver SDI1 is used to receive serial data into the RX1 serial receive shift register PE7 Input Output or Disconnected GPIO Port E7 When the ESAI_1 is configured as GPIO PE7 is individually programmable as input output or internally disc...

Page 40: ...iver SDI0_2 is used to receive serial data into the RX0 serial receive shift register PC6_1 Input Output or Disconnected GPIO Port C6_1 When the ESAI_2 is configured as GPIO PC6_1 is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Uses internal pull down resistor in the DSP56724 144 pin package Uses internal pull up resistor i...

Page 41: ...DSP56724 144 pin package Uses internal pull up resistor in DSP56725 80 pin and 144 pin packages SDO2_2 Output GPIO Disconnected ESAI_2 s Serial Data Output 2 When programmed as a transmitter SDO2_2 is used to transmit data from the TX2 serial transmit shift register SDI3_2 Input ESAI_2 s Serial Data Input 3 When programmed as a receiver SDI3_2 is used to receive serial data into the RX3 serial rec...

Page 42: ... this clock is generated by the internal S PDIF s DPLL S PDIF Receive Clock output controlled by the ERC3 bits in Pin MUX Control Register of the Chip Configuration Module The default state after reset is GPIO disconnected Uses an internal pull down resistor HCKT_3 Input or Output GPIO Disconnected ESAI_3 s High Frequency Clock for Transmitter When programmed as an input HCKT_3 provides a high fre...

Page 43: ...red in the IF1 bit in the SAISR register synchronized by the frame sync in normal mode or by the slot in network mode PE1_1 Input Output or Disconnected GPIO Port E1_1 When the ESAI_3 is configured as GPIO PE1_1 is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Uses an internal pull down resistor FST_3 Input or Output GPIO Di...

Page 44: ...sistor SCKT_3 Input or Output GPIO Disconnected ESAI_3 s Transmitter Serial Clock SCKT_3 provides the serial bit rate clock for the ESAI_3 SCKT_3 is a clock input or output used by all enabled transmitters and receivers in synchronous mode or by all enabled transmitters in asynchronous mode PE3_1 Input Output or Disconnected GPIO Port E3_1 When the ESAI_3 is configured as GPIO PE3_1 is individuall...

Page 45: ...l data into the RX2 serial receive shift register PE8_1 Input Output or Disconnected GPIO Port E8_1 When the ESAI_3 is configured as GPIO PE8_1 is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Uses an internal pull down resistor in the DSP56724 144 pin package Uses an internal pull up resistor in the DSP56725 80 pin package ...

Page 46: ...k WDT pin is used by DSP Core 0 Table 2 17 WDT Signal Signal Name Type State after Reset Description WDT Output WDT output This signal is asserted low when the hardware watchdog timer counts down to zero This pin is controlled by both WDT and WDT_1 modules and is asserted when the watchdog timer counts down to zero in either WDT or WDT_1 modules ...

Page 47: ... provided Asserted Negated Used to enable specific memory devices or peripherals connected to the EMC LCS 7 0 are provided on a per bank basis with LCS0 corresponding to the chip select for memory bank 0 which has the memory type and attributes defined by BR0 and OR0 Uses an internal pull up resistor LWE LSDDQM Output LWE LSDDQM GPCM Write Enable SDRAM Data Mask Asserted Negated For GPCM operation...

Page 48: ... Buffer Control When a GPCM or UPM controlled bank is accessed the memory controller activates a data buffer control signal BCTL for the external memory Access to an SDRAM machine controlled bank does not activate the buffer control The buffer control can be disabled by setting ORx BCTLD Asserted Negated The LBCTL pin normally functions as a Write Read control for a bus transceiver connected to th...

Page 49: ... LAD0 The default state after reset for these signals is GPIO disconnected Internal Pull Down Resistor for these signals LCKE Output LCKE External Memory Clock Enable Asserted Negated LCKE is the bus clock enable signal CKE for JEDEC standard SDRAM devices This signal is asserted during normal SDRAM operation Uses an internal pull up resistor LCLK Output LCLK External Memory Clocks Asserted Negate...

Page 50: ...rk format Consumer C channel PG13 Input or Output or Disconnected GPIO Port G13 When the S PDIF is configured as GPIO these signals are individually programmable as input output or internally disconnected This signal can used by the GPIO port G function GPIO functions are controlled by GPIO port G registers There is a bit in the chip configuration registers that set it to S PDIF The default state ...

Page 51: ... Signal Type State During Reset Description TCK Input Input Test Clock TCK is a test clock input signal used to synchronize the JTAG test logic It uses an internal pull up resistor TDI Input Input Test Data Input TDI is a test data serial input signal used for test instructions and data TDI is sampled on the rising edge of TCK and uses an internal pull up resistor TDO Output Tri Stated Test Data O...

Page 52: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 2 30 Freescale Semiconductor Signal Descriptions ...

Page 53: ...RAM Program X and Y RAM allocation on each DSP can be configured as five types of memory maps a default mode plus four additional memory maps based on two bit settings MSW0 MSW1 Four blocks of 8K shared memory RAM are accessible in the DSP56724 DSP56725 The shared memory blocks occupy addresses from 030000 to 037FFF including 037FFF accessible by both DSP cores When the DSP cores access the shared...

Page 54: ...W1 bit Table 3 1 Core 0 Configuration Bit Settings Memory Space MSW1 MSW0 MS Program RAM X Data RAM Y Data RAM 0 4 K 28 K 24 K 0 0 1 40 K 8 K 8 K 0 1 1 24 K 16 K 16 K 1 0 1 16 K 24 K 16 K 1 1 1 8 K 24 K 24 K Table 3 2 Core 1 Configuration Bit Settings Memory Space MSW1 MSW0 MS Program RAM X Data RAM Y Data RAM 0 2 K 12 K 10 K 0 0 1 16 K 4 K 4 K 0 1 1 12 K 8 K 4 K 1 0 1 8 K 8 K 8 K 1 1 1 4 K 12 K 8...

Page 55: ...SP Core 0 is PIC while DSP Core 1 is PIC_1 MSW1 0 MSW0 1 MS 1 24 K 16 K 16 K 000000 005FFF 000000 003FFF 000000 003FFF MSW1 0 MSW0 0 MS 1 40 K 8 K 8 K 000000 009FFF 000000 001FFF 000000 001FFF Table 3 4 DSP Core 1 Memory Map Locations Configuration Program RAM X Data RAM Y Data RAM MSW NA MS 0 2 K 12 K 10 K 1 2K block 3 4 K block 1 4 K block 000000 007FFF 000000 002FFF 000000 0027FF MSW1 1 MSW0 1 ...

Page 56: ... port H X FF_FF97 FF_FF90 SHI SHI_1 X FF_FF8F FF_FF80 Triple Timer TEC Triple Timer TEC_1 X FF_FF7F FF_FF7C CGM X FF_FF7B FF_FF78 Reserved X FF_FF77 FF_FF60 S PDIF X FF_FF5F FF_FE6C Reserved X FF_FE6B FF_FE00 EMC X FF_FDFF FF_E000 Reserved Table 3 6 Y Memory Map for DSP Core 0 and Core 1 Address Range Blocks DSP Core 0 DSP Core 1 Y FF_FFFF FF_FFF8 GPIO Port G Y FF_FFF7 FF_FFF0 GPIO Port A Y FF_FFE...

Page 57: ...FFC OnCE Global Data Register OGDB PIC PIC_1 X FF_FFFB Interrupt Priority Register Core IPR_C1 X FF_FFFA Interrupt Priority Register Peripheral IPR_P1 X FF_FFF9 Reserved CIM CIM_1 X FF_FFF8 DMA stall register DMAS X FF_FFF6 Reserved X FF_FFF5 CHIP ID Register CHIDR DMA DMA_1 X FF_FFF4 DMA Status Register DSTR X FF_FFF3 DMA Offset Register 0 DOR0 X FF_FFF2 DMA Offset Register 1 DOR1 X FF_FFF1 DMA O...

Page 58: ...ster DSR4 X FF_FFDE DMA Destination Address Register DDR4 X FF_FFDD DMA Counter DCO4 X FF_FFDC DMA Control Register DCR4 DMA DMA_1 Channel 5 X FF_FFDB DMA Source Address Register DSR5 X FF_FFDA DMA Destination Address Register DDR5 X FF_FFD9 DMA Counter DCO5 X FF_FFD8 DMA Control Register DCR5 DMA DMA_1 Channel 6 X FF_FFD7 DMA Source Address Register DSR6 X FF_FFD6 DMA Destination Address Register...

Page 59: ...FFB2 to X FF_FFAC Reserved X FF_FFAB ESAI ESAI_2 Receive Data Register 3 RX3 X FF_FFAA ESAI ESAI_2 Receive Data Register 2 RX2 X FF_FFA9 ESAI ESAI_2 Receive Data Register 1 RX1 X FF_FFA8 ESAI ESAI_2 Receive Data Register 0 RX0 X FF_FFA7 Reserved X FF_FFA6 ESAI ESAI_2 Time Slot Register TSR ESAI ESAI_2 X FF_FFA5 ESAI ESAI_2 Transmit Data Register 5 TX5 X FF_FFA4 ESAI ESAI_2 Transmit Data Register 4...

Page 60: ... Control Status Register TCSR1 X FF_FF8A Timer 1 Load Register TLR1 X FF_FF89 Timer 1 Compare Register TCPR1 X FF_FF88 Timer 1 Count Register TCR1 X FF_FF87 Timer 2 Control Status Register TCSR2 X FF_FF86 Timer 2 Load Register TLR2 X FF_FF85 Timer 2 Compare Register TCPR2 X FF_FF84 Timer 2 Count Register TCR2 X FF_FF83 Timer Prescaler Load Register TPLR X FF_FF82 Timer Prescaler Count Register TPC...

Page 61: ...DIF Transmit Right Channel STR X FF_FF6B S PDIF Transmit Left Channel STL X FF_FF6A S PDIF Receiver Q Channel SRQ X FF_FF69 S PDIF Receiver U Channel SRU X FF_FF68 S PDIF Receiver Channel Status 24 47 SRCSL X FF_FF67 S PDIF Receiver Channel Status 00 23 SRCSH X FF_FF66 S PDIF Receiver Right SRR X FF_FF65 S PDIF Receiver Left SRL X FF_FF64 S PDIF Interrupt STAT CLR SIS SIC X FF_FF63 S PDIF Interrup...

Page 62: ...RH X FF_FE5E EMC Transfer Error Attributes Register low part TEATRL X FF_FE5D EMC Transfer Error Interrupt Register TEIR X FF_FE5C Reserved X FF_FE5B EMC Transfer Error Disable Register TEDR X FF_FE5A Reserved X FF_FE59 EMC Transfer Error Status Register TESR X FF_FE58 Reserved X FF_FE57 to X FF_FE54 Reserved X FF_FE53 SDRAM Refresh Timer SRT X FF_FE52 Reserved X FF_FE51 EMC UPM Refresh Timer URT ...

Page 63: ...FF_FE20 Reserved X FF_FE1F EMC Options Register 7 high part ORH7 X FF_FE1E EMC Options Register 7 low part ORL7 X FF_FE1D EMC Base Register 7 high part BRH7 X FF_FE1C EMC Base Register 7 low part BRL7 X FF_FE1B EMC Options Register 6 high part ORH6 X FF_FE1A EMC Options Register 6 low part ORL6 X FF_FE19 EMC Base Register 6 high part BRH6 X FF_FE18 EMC Base Register 6 low part BRL6 X FF_FE17 EMC O...

Page 64: ...egister 1 high part BRH1 X FF_FE04 EMC Base Register 1 low part BRL1 X FF_FE03 EMC Options Register 0 high part ORH0 X FF_FE02 EMC Options Register 0 low part ORL0 X FF_FE01 EMC Base Register 0 high part BRH0 X FF_FE00 EMC Base Register 0 low part BRL0 X FF_FDFF to X FF_F000 Reserved 1 Includes short name and long name Table 3 8 Detailed Device Y Memory Map Peripherals Address Register Name1 GPIO ...

Page 65: ...r PRRA Y FF_FFF0 Port A GPIO Data Register PDRA Y FF_FFEF to Y FF_FFE7 Reserved Chip Configuration Y FF_FFE6 External Memory Burst Control Register EMBC Y FF_FFE5 EMC PLL Status Control Register PSC Y FF_FFE4 Chip Pin Mux Control PMCR Y FF_FFE3 ESAI Pin Switch Control Register EPSC Y FF_FFE2 Once Debug and Burst Control Register ODBC Y FF_FFE1 Shared Peripheral Software Reset Control Register SPSR...

Page 66: ...askable interrupt to the other core Y FF_FFD4 ICC Data Register 4 ICDR4 For maskable Interrupt from the other core Y FF_FFD3 ICC Control Register 4 ICCR4 For maskable Interrupt from the other core Y FF_FFD2 ICC Acknowledge Register 4 ICAR4 Acknowledge for the maskable interrupt from the other core Y FF_FFD1 ICC Poll Register 1 ICPR1 Read poll data from the other core Y FF_FFD0 ICC Poll Register 2 ...

Page 67: ... Register SAICR_1 Y FFFF93 ESAI_1 3 Status Register SAISR_1 Y FFFF92 to Y FFFF8C Reserved Y FFFF8B ESAI_1 3 Receive Data Register 3 RX3_1 Y FFFF8A ESAI_1 3 Receive Data Register 2 RX2_1 Y FFFF89 ESAI_1 3 Receive Data Register 1 RX1_1 Y FFFF88 ESAI_1 3 Receive Data Register 0 RX0_1 Y FFFF87 Reserved Y FFFF86 ESAI_1 3 Time Slot Register TSR_1 3 Y FFFF85 ESAI_1 3 Transmit Data Register 5 TX5_1 Y FFFF...

Page 68: ... Control Register 1 ASRDCR 1 Y FF_FC0E Debug Control Register ASRDCR Y FF_FC0D Memory Access Data Register ASRMAD Y FF_FC0C Memory Access Address Register ASRMAA Y FF_FC0B to Y FF_FC09 Reserved Y FF_FC08 ASRC Status Register ASRSTR Y FF_FC07 ASRC Clock Divider Register ASRCDR 2 Y FF_FC06 ASRC Clock Divider Register ASRCDR 1 Y FF_FC05 ASRC Clock Source Register ASRCSR Y FF_FC04 Filter Configuration...

Page 69: ...300 Platform 4 1 Overview The DSP56724 and DSP56725 have two DSP56300 platforms which are identical Each DSP56300 platform includes a DSP56300 core a direct memory access unit DMA a program interrupt controller PIC and a Core DMA Arbiter Figure 4 1 provides the block diagram for the DSP56300 Core in DSP56724 and DSP56725 ...

Page 70: ... new level of performance in speed and power provided by its rich instruction set and low power dissipation thus enabling a new generation of wireless telecommunications and multimedia products Significant architectural enhancements to the DSP56300 core family include a OnCE Address Generate Unit AGU Internal Data Bus Switch Internal Memory Blocks RAMs ROMs Program Control Unit PCU Direct Memory A...

Page 71: ... Block Descriptions The DSP56300 core provides five main functional blocks Data arithmetic logic unit Data ALU Address generation unit AGU Program control unit PCU Internal Data Bus Switch OnCE module DSP56300 core features are described fully in the DSP56300 Family Manual 4 3 1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core Data ALU ...

Page 72: ...A or B accumulator A 56 bit result can be stored as a 24 bit operand The LSP can either be truncated or rounded into the MSP Rounding is performed if specified 4 3 2 Address Generation Unit AGU The Address Generation Unit performs effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses The AGU im...

Page 73: ... as well as the five external requests IRQA IRQB IRQC IRQD and NMI and generates the appropriate interrupt vector address PCU features include Position independent code support Addressing modes optimized for DSP applications including immediate offsets On chip instruction cache controller On chip memory expandable hardware stack Nested hardware DO loops Fast auto return interrupts The PCU implemen...

Page 74: ...al shared memory mapped peripherals or memory The Shared Bus is an enhanced feature which replaces the Port A external memory interface from the DSP56300 family All accesses via the Shared Bus behave as a zero wait state SSRAM access from the Port A external memory interface potentially extended by a transfer acknowledge For this reason all Program memory accesses by the DSP core over the Shared B...

Page 75: ...e DSP56300 core see the DSP56300 Family Manual DSP56300FM 5 2 Operating Mode Register OMR Both DSP cores have the operating mode register OMR as shown in Table 5 1 See the DSP56300 Family Manual DSP56300FM for a description of the all of the OMR bits Table 5 1 Operating Mode Register OMR SCS EOM COM 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSW 1 0 SEN WRP EOV EUN XYS CDP1 0 MS...

Page 76: ... Operation Mode Register Bit Definitions Bit Number Bit Name Reset Value Description 23 0 Reserved Write to zero for future compatibility 22 21 MSW1 MSW0 0 Memory Switch Mode 1 Memory Switch Mode 0 See the DSP56300 FM 5 4 1 1 Operation Mode Register OMR and Chapter 3 of this document 20 SEN 0 Stack Extension Enable See the DSP56300 FM 5 4 1 1 Operation Mode Register OMR 19 WRP 0 Extended Stack Wra...

Page 77: ...ster MR for example ANDI ORI or instructions such as MOVEC that specify the Status Register SR as the destination During hardware reset the interrupt mask bits are set and all other bits are cleared Condition Code Register CCR SR 7 0 Defines the results of previous arithmetic computations The CCR register bits are affected by Data Arithmetic Logic Unit Data ALU operations parallel move operations ...

Page 78: ...mpared against the priority bits of the active DMA channel If the core priority is greater than the DMA priority the DMA waits for a free time slot on the external shared bus If the core priority is less than the DMA priority the core waits for a free time slot on the external shared bus If the core priority equals the DMA priority the core and DMA take turns accessing in a round robin pattern for...

Page 79: ...ore executing an RTI instruction 17 SA 0 Sixteen Bit Arithmetic Mode See the DSP56300 Family Manual 5 4 1 2 Status Register SR 16 FV 0 DO FOREVER Flag See the DSP56300 Family Manual 5 4 1 2 Status Register SR 15 LF 0 DO Loop Flag See the DSP56300 Family Manual 5 4 1 2 Status Register SR 14 12 0 Reserved Write to zero for future compatibility 11 10 S 1 0 0 Scaling Mode See the DSP56300 Family Manua...

Page 80: ...4 External Pins Reset Vector Description MODD0 MODC0 MODB0 MODA0 OMR MD OMR MC OMR MB OMR MA 0 0 0 0 0 FF_FFFE Boot via SHI SPI 1 0 0 0 1 Boot via SHI I2C Filter 2 0 0 1 0 Jump to PROM SPI 3 0 0 1 1 Jump to PROM I2C Filter 4 0 1 0 0 Boot via Core 1 5 0 1 0 1 Boot via SHI Master SPI EEPROM 6 0 1 1 0 Boot via SHI Master I2C EEPROM 7 0 1 1 1 Boot via GPIO Master SPI EEPROM PE6 PE7 PE8 PE9 8 1 0 0 0 B...

Page 81: ...d Table 5 7 DSP56724 Core 0 Core 1 Boot Modes Mode Name Description Mode 0 Boot via SHI SPI In Mode 0 the internal PRAM is loaded from the Serial Host Interface SHI The SHI operates in the SPI slave mode with 24 bit word width The bootstrap code expects to read a single 24 bit word specifying the number of program words another 24 bit word specifying the address to start loading the program words ...

Page 82: ...via SHI Master I2C EEPROM In Mode 6 the internal memory PRAM XRAM or YRAM is loaded from an external serial EPROM in I2 C mode with the 100 ns filter enabled Mode 6 supports using ST M24256 and the Atmel AT24C256 memories Mode 7 Boot via GPIO SPI EEPROM FLASH In Mode 7 the internal memory PRAM XRAM or YRAM is loaded from an external serial EPROM in SPI mode via the GPIO pins Core 0 GPIO pins PE6 C...

Page 83: ...DMA channels interrupts only 2 additional DMA channels are used in the DSP56724 DSP56725 IPR P1 is dedicated for an additional 12 peripheral interrupt sources only parts of the additional interrupts are used in the DSP56724 DSP56725 The Interrupt Priority registers are shown in Figure 5 1 through Figure 5 8 The Interrupt Priority Level bits are defined in Table 5 8 and Table 5 9 The interrupt prio...

Page 84: ...PL TRIPLE TIMER IPL ESL10 SPDIF Rx IPL SPRL0 SPRL1 SPTL0 SPTL1 ICIL0 ICIL1 ICAL0 ICAL1 ASL0 ASL1 SPDIF Tx IPL ASRC Rx IPL ICC INT IPL ICC ACK INT IPL LIEL0 LIEL1 IAL0 IAL1 IAL2 IBL0 IBL1 IBL2 ICL0 ICL1 ICL2 0 1 2 3 4 5 6 7 8 9 10 11 IRQA IPL IRQA mode IRQB IPL IRQB mode IRQC IPL IRQC mode IRQD IPL D0L0 D0L1 D1L0 D1L1 23 22 21 20 19 18 17 16 15 14 13 12 DMA ch0 IPL DMA ch1 IPL D2L0 D2L1 D3L0 D3L1 D...

Page 85: ...16 15 14 13 12 0 1 2 3 4 5 6 7 8 9 10 11 ESAI_2 IPL SHI_1 IPL Reserved ESAI_3 IPL ESL31 TAL10 TAL11 EMC ICC Error INT IPL TIMER_1 IPL ESL30 SPDIF Rx IPL SPRL0 SPRL1 SPTL0 SPTL1 ICIL0 ICIL1 ICAL0 ICAL1 ASL0 ASL1 SPDIF Tx IPL ASRC Rx IPL ICC INT IPL ICC ACK INT IPL LIEL0 LIEL1 Reserved IAL0 IAL1 IAL2 IBL0 IBL1 IBL2 ICL0 ICL1 ICL2 0 1 2 3 4 5 6 7 8 9 10 11 IRQA IPL IRQA mode IRQB IPL IRQB mode IRQC I...

Page 86: ...rce Group Level 3 non maskable Highest RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non Maskable Interrupt NMI from External DMA Stall Interrupt Lowest Inter Core Non Maskable Interrupt from the other core Level 0 2 maskable D6L0 D6L1 D7L0 D7L1 0 1 2 3 4 5 6 7 8 9 10 11 DMA1 ch6 IPL DMA1 ch7 IPL 13 12 14 15 16 17 18 19 20 21 22 23 Reserved Reserved 0 1 2 3 4 5 6 7 8 9 10 11 1...

Page 87: ... ESAI_2 ESAI ESAI_2 Receive Even Data ESAI ESAI_2 Receive Data ESAI ESAI_2 Receive Last Slot ESAI ESAI_2 Transmit Data with Exception Status ESAI ESAI_2 Transmit Last Slot ESAI ESAI_2 Transmit Even Data ESAI ESAI_2 Transmit Data SHI SHI_1 Bus Error SHI SHI_1 SHI SHI_1 Receive Overrun Error SHI SHI_1 Transmit Underrun Error SHI SHI_1 Receive FIFO Full SHI SHI_1 Transmit Data SHI SHI_1 Receive FIFO ...

Page 88: ...1 3 Transmit Data ESAI_1 3 Transmit Even Data ESAI_1 3 Transmit Data with Exception Status ESAI_1 3 Transmit Last Slot S PDIF RcvChannelNew S PDIF S PDIF RcvValidityBitNotSet S PDIF RcvIllegalSymbol S PDIF RcvParityError S PDIF RxUChannelFull S PDIF RxUChannelOver S PDIF RxQChannelFull S PDIF RxQChannelOver S PDIF RxUQSyncFound S PDIF RxUQFrameError S PDIF Rx Over Under S PDIF Rx Resync S PDIF Loc...

Page 89: ...rupt from the other core EMC ICC Access Error Interrupt Lowest Always Active Interrupt Table 5 11 Reset and Interrupt Vector Summary Interrupt Starting Address Priority Level Range Description Notes VBA 00 3 RESET VBA 02 3 Stack Error VBA 04 3 Illegal Instruction VBA 06 3 Debug Request Interrupt VBA 08 3 Trap VBA 0A 3 Non Maskable Interrupt NMI external VBA 0C 3 Reserved VBA 0E 3 DMA Stall Interru...

Page 90: ...AI Output interrupts to Core 0 ESAI_2 Output interrupts to Core 1 VBA 32 0 2 ESAI ESAI_2 Receive Even Data VBA 34 0 2 ESAI ESAI_2 Receive Data With Exception VBA 36 0 2 ESAI ESAI_2 Receive Last Slot VBA 38 0 2 ESAI ESAI_2 Transmit Data VBA 3A 0 2 ESAI ESAI_2 Transmit Even Data VBA 3C 0 2 ESAI ESAI_2 Transmit Data with Exception Status VBA 3E 0 2 ESAI ESAI_2 Transmit Last Slot VBA 40 0 2 SHI SHI_1 ...

Page 91: ... 2 Reserved VBA 62 0 2 VBA 66 0 2 Reserved VBA 68 0 2 VBA 6A 0 2 VBA 6C 0 2 VBA 6E 0 2 VBA 70 0 2 ESAI_1 3 Receive Data ESAI_1 Output interrupts to Core 0 ESAI_3 Output interrupts to Core 1 VBA 72 0 2 ESAI_1 3 Receive Even Data VBA 74 0 2 ESAI_1 3 Receive Data With Exception VBA 76 0 2 ESAI_1 3 Receive Last Slot VBA 78 0 2 ESAI_1 3 Transmit Data VBA 7A 0 2 ESAI_1 3 Transmit Even Data VBA 7C 0 2 ES...

Page 92: ...2 S PDIF Lock Loss VBA 9A 0 2 S PDIF Rcv FIFO Full VBA 9C 0 2 S PDIF Lock Interrupt VBA 9E 0 2 Reserved VBA A0 0 2 S PDIF Tx Over Under VBA A2 0 2 S PDIF Tx Resync VBA A4 0 2 Reserved VBA A6 0 2 Reserved VBA A8 0 2 Reserved VBA AA 0 2 S PDIF Tx FIFO Empty VBA AC to VBA AE 0 2 Reserved VBA B0 0 2 ASRC Data Input A Interrupt ASRC VBA B2 0 2 ASRC Data Input B Interrupt VBA B4 0 2 ASRC Data Input C In...

Page 93: ... DMA status register is slightly different with 8 channels of DMA DSTR 6 DTD6 DMA channel 6 the seventh channel transfer has finished DSTR 7 DTD7 DMA channel 7 the eighth channel transfer has finished DSTR 10 9 DCH 2 0 when DCH 2 0 6 it indicates that the active channel is DMA channel 6 when DCH 2 0 7 it indicates that the active channel is DMA channel 7 Table 5 12 shows the DMA request sources fo...

Page 94: ...3 Reserved 0_1010 0_1010 14 ESAI ESAI_2 receive data RDF 1 0_1011 0_1011 15 ESAI ESAI_2 transmit data TDE 1 0_1100 0_1100 16 SHI HTX Empty 0_1101 0_1101 17 SHI FIFO Not Empty 0_1110 0_1110 18 SHI FIFO Full 0_1111 0_1111 19 TIMER0 1_0010 1_0010 20 TIMER1 1_0011 1_0011 21 TIMER2 1_0100 1_0100 22 ESAI_1 ESAI_3 Receive Data RDF 1 1_0101 1_0101 23 ESAI_1 ESAI_3 Transmit Data TDE 1 1_0110 1_0110 24 S PD...

Page 95: ...register OnCE global data bus GDB register and DMA Stall register In more detail The Chip ID Register contains the chip ID number The CIM includes a DMA Monitor that optionally supports a non maskable interrupt after the DMA has been stalled due to internal memory contention for more than N cycles where N can be from 2 to 224 cycles The OnCE GDB register is a 24 bit register that can be read throu...

Page 96: ...R W 0x000000 X FFFFFC OnCE Global Data Bus Register OGDB R W 0x000000 Table 6 2 CIM Register Summary Register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSP56724 Core 0 Chip ID Register CHIDR X FFFFF5 R 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 1 1 1 0 0 1 0 0 0 0 0 W DSP56724 Core 1 Chip ID Register CHIDR X FFFFF5 R 0 0 0 0 0 0 0 1 0 0 0 0 W R 0 1 1 1 0 0 1 0 0 0 0 0 W 1 Always reads 1 0 A...

Page 97: ...ip ID Register value is 0x000725 for Core 0 and 0x010725 for Core 1 DSP56725 Core 0 Chip ID Register CHIDR X FFFFF5 R 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 1 1 1 0 0 1 0 0 0 0 1 W DSP56725 Core 1 Chip ID Register CHIDR X FFFFF5 R 0 0 0 0 0 0 0 1 0 0 0 0 W R 0 1 1 1 0 0 1 0 0 0 0 1 W DMA Stall Register DMAS Y FFFFF8 R D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 W R D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0...

Page 98: ... Core 0 CHIDR R 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 1 1 1 0 0 1 0 0 0 0 0 W Table 6 4 Chip ID Register for DSP56724 Core 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip ID Register for DSP56724 Core 1 CHIDR R 0 0 0 0 0 0 0 1 0 0 0 0 W R 0 1 1 1 0 0 1 0 0 0 0 0 W Table 6 5 Chip ID Register for DSP56725 Core 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip ID Regis...

Page 99: ...asserted until the internal memory contention ends usually due to the interrupt routine or until the DMA Stall Register is written with zero The stall counter clears when the internal memory contention ends or when the DMA Stall Register is written with zero 6 2 3 OnCE Global Data Bus Register OGDB The OnCE GDB Register is 24 bit read write register that can be read through the JTAG port and is us...

Page 100: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 6 6 Freescale Semiconductor Core Integration Module CIM CIM_1 ...

Page 101: ...bus In the CGM the PLL control register PCTL which sits on the shared peripheral bus can be read and written by both DSP cores to change the device s working frequency Each DSP core can enter the STOP or WAIT mode for power saving The shared peripherals the shared memory block and the external memory interface if present can enter power saving mode only when both cores enter STOP mode NOTES A rese...

Page 102: ...SP56724 DSP56725 devices For stable operations the system clock is defined in Table 7 1 PLL Control Registers Internal PLL Clock input division Frequency multiplication Skew elimination CGM Extal PLL Out FOUT raw Low Power Divider 2i i 0 7 internal_clk Core 0 Stop or Wait mode Core 1 Stop or Wait mode Core 0 Gating Cells Core 1 Gating Cells Shared Gating Cells Clocks to Core 0 Clocks to Core 1 Clo...

Page 103: ...s always active for proper switching and wake up System Clock2 2 System Clock the clock used by all DSP56724 DSP56725 modules Core Cock Peripheral Clock During Reset pinit_nmi 1 0 1 By default 03 3 The PLL LD will be low if the PLL doesn t detect a lock condition Fosc Fosc Fosc pinit_nmi 0 After Reset PLL Normal mode4 4 The mode that PLL will get into after reset normal mode or bypass mode is deci...

Page 104: ...erties Signal Name Function I O Reset Pull Up PINIT During assertion of a hardware reset the value of the PINIT input pin is written into the PCTL PLL Enable PEN bit After a hardware reset is de asserted the PLL ignores the PINIT pin The default PCTL setting when PINIT is asserted is 2B60C2 Input Input Pull Up EXTAL An external clock is required to drive the DSP The external clock is input via the...

Page 105: ...ider setting of R 4 0 F 7 0 and OD 1 0 When the divider settings are changed the PLL must enter the power down mode PD HIGH for more than 50 ns a PD timing requirement see Table 7 3 Bypass Mode The FIN is buffered directly to FOUT bypassing the PLL which is powered down A TRDY time pull in lock time is required for the PLL to lock when switching from Bypass Mode to Normal Mode Power down Mode The ...

Page 106: ...put Clock Frequency The following equations describe how the output frequency is calculated FREF FIN NR Eqn 7 1 FVCO FOUT NO Eqn 7 2 FOUT FIN NF NR NO Eqn 7 3 where FREF is the comparison frequency for the PFD For proper operation in normal mode the following constraints must be satisfied When programming the Output Clock Frequency 2 MHz Fref 8 MHz 200 MHz Fvco 500 MHz See Table 7 9 7 2 5 Low Powe...

Page 107: ... Page X FFFF_7C SPENA Shared Peripheral Clock Enable Registers R W 0x00_0001 7 3 3 1 7 7 X FFFF_7D PCTL PLL Control Registers R W 0x2B_60C21 1 The default value of PCTL should be 0x2B_60C2 if PINIT 1 during reset 7 3 3 2 7 8 X FFFF_7E ASCDR ASRC Control Division Registers R W 0x00_0022 7 3 3 3 7 11 Table 7 6 Register Summary Name 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFFF...

Page 108: ...on the ASRC clock Address 0xBASE_7D PCTL Access Read Write Bit 23 22 21 20 19 18 17 16 15 14 13 12 R W PLKM R4 R3 R2 R1 R0 OD1 OD0 PEN PSTP Reset 0 0 1 0 1 0 1 1 0 1 TINIT1 1 Reset value of PEN is 1 when TINIT is set reset value of PEN is 0 when TINIT is cleared 1 Bit 11 10 9 8 7 6 5 4 3 2 1 0 R W DF2 DF1 DF0 F7 F6 F5 F4 F3 F2 F1 F0 Reset 0 0 0 0 1 1 0 0 0 0 1 0 Figure 7 4 PLL Control Register PCT...

Page 109: ...stal oscillator behavior during the Stop processing state When PSTP is set the PLL remains operating while the chip is in the Stop state When PSTP is cleared and the device enters the Stop state the PLL is disabled to further reduce power consumption PSTP PEN 2 b0x PLL disabled Only in system Stop mode PSTP PEN 2 b10 PLL is enabled always but is in bypass mode PSTP PEN 2 b11 PLL is enabled always ...

Page 110: ...4 2B60B4 24 576 12 2 048 171 350 208 2 175 104 2B60AA 24 576 12 2 048 157 321 536 2 160 768 2B609C 24 576 12 2 048 180 368 640 2 184 320 2B60B3 24 576 12 2 048 147 301 056 2 150 528 2B6092 24 576 12 2 048 98 200 704 8 25 088 2BE061 24 576 4 6 144 65 399 360 2 199 680 236040 24 576 4 6 144 33 202 752 1 202 752 234020 12 288 6 2 048 98 200 704 1 200 704 254061 12 288 6 2 048 195 399 360 2 199 680 25...

Page 111: ...lock Dividing Control Register ASCDR Address 0xBASE_7E ASCDR Access Read Write Bit 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset Bit 11 10 9 8 7 6 5 4 3 2 1 0 R W ASDF6 ASDF5 ASDF4 ASDF3 ASDF2 ASDF1 ASDF0 Reset 0 1 0 0 0 1 0 Table 7 11 ASRC Control Division Registers Field Description Bits Field Description 6 0 ASDF6 ASDF0 ASRC Divider Factor Defines the division factor of asrc_divider This divide...

Page 112: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 7 12 Freescale Semiconductor Clock Generation Module CGM ...

Page 113: ...manual describes the special uses of these signals in detail There are ten groups of these signals which can be controlled separately or as groups See Table 8 1 Table 8 1 GPIO Pins Summary Table GPIO Group Function Shared Pins Available Pins in Different Packages DSP5724 DSP56725 144 Pin 80 Pin 1 Port C Shared with ESAI signals 10 10 2 Port H Shared with SHI signals 1 1 3 Port E Shared with ESAI_1...

Page 114: ... register PRRE Port E data register PDRE Port C1 ESAI_2 Signal Port C1 control register PCRC1 Port C1 direction register PRRC1 Port C1 data register PDRC1 Port E1 ESAI_3 Signal Port E control register PCRE1 Port E direction register PRRE1 Port E data register PDRE1 8 2 2 Port H Signals and Registers The SHI s HREQ can be configured as a GPIO signal The GPIO functionality of Port H is controlled by...

Page 115: ...gured as GPIO If a port pin i is configured as a GPIO input then the corresponding PD i bit reflects the value present on this pin If a port pin i is configured as a GPIO output then the value written into the corresponding PD i bit is reflected on this pin If a port pin i is configured as disconnected then the corresponding PD i bit does not reflect the value present on this pin Table 8 2 PCRH an...

Page 116: ...he EXTAL clock is directed to the HCKT_1 pin When the ETO1 bit is cleared the EXTAL clock is not directed to the HCKT_1 pin ERI1 When the ERI1 bit is set the EXTAL clock can be used to generate the ESAI_1 receiver clocks HCKR_1 SCKR_1 and FSR_1 When the ERI1 bit is cleared the Fosc clock can be used to generate the ESAI_1 transmitter clocks HCKR_1 SCKR_1 and FSR_1 ERO1 When the ERO1 bit is set the...

Page 117: ...er PRRH1 and the Port H1 Control Register PCRH1 together control the functionality of the dedicated GPIO pins For the port pin configuration see Table 8 5 Hardware and software reset sets all PRRH1 bits Table 8 5 PCRH1 and PRRH1 Bits Functionality PDH1 i PH1 i Port Pin i Function 0 0 Disconnected 0 1 GPIO input 1 0 GPIO output 1 1 Respective Functionality SHI_1 s HREQ Table 8 6 PORT H1 Registers S...

Page 118: ...1 bit is cleared the Fosc clock can be used to generate the ESAI_3 transmitter clocks HCKT_3 SCKT_3 and FST_3 ETO3_1 When the ETO3_1 bit is set the EXTAL clock is directed to the HCKT_3 pin When the ETO3_1 bit is cleared the EXTAL clock is not directed to the HCKT_3 pin ERI3_1 When the ERI3_1 bit is set the EXTAL clock can be used to generate the ESAI_3 receiver clocks HCKR_3 SCKR_3 and FSR_3 When...

Page 119: ...9 8 7 6 5 4 3 2 1 0 PDRA Y FFFFF0 R W PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 Reset 0 0 0 0 0 0 0 0 0 0 0 0 R W PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 PRRA Y FFFFF1 R W PDA23 PDA22 PDA21 PDA20 PDA19 PDA18 PDA17 PDA16 PDA15 PDA14 PDA13 PDA12 Reset 0 0 0 0 0 0 0 0 0 0 0 0 R W PDA11 PDA10 PDA9 PDA8 PDA7 PDA6 PDA5 PDA4 PDA3 PDA2 PDA1 PDA0 Re...

Page 120: ...PDRA1 The read write 24 bit Port A Data Registers PDRA PDRA1 are used to read write data from to the dedicated GPIO pins Bits PD 47 0 are used to read write data from to the corresponding port pins if they are configured as GPIO If a port pin i is configured as a GPIO input then the corresponding PD i bit reflects the value present on this pin If a port pin i is configured as a GPIO output then th...

Page 121: ...0 0 0 0 0 R W PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD3 PD2 PD1 PD0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 PRRG Y FFFFF9 R W PDG21 PDG20 PDG19 PDG18 PDG15 PDG14 PDG13 PDG12 Reset 0 0 0 0 0 0 0 0 0 0 0 0 R W PDG11 PDG10 PDG9 PDG8 PDG7 PDG6 PDG5 PDG3 PDG2 PDG1 PDG0 Reset 0 0 0 1 1 1 1 0 0 0 0 1 PCRG Y FFFFFA R W PG21 PG20 PG19 PG18 PG15 PG14 PG13 PG12 Reset 0 0 0 0 0 0 0 0 0 0 0 0 R W PG11 PG10 PG9 PG8 PG7 PG6 PG5 P...

Page 122: ...er reset 8 2 5 3 Port G Data Register PDRG PDRG1 The read write 24 bit Port G Data Registers PDRG PDRG1 are used to read write data from to the dedicated GPIO pins Bits PD 39 0 are used to read write data from to the corresponding port pins if they are configured as GPIO If a port pin i is configured as a GPIO input then the corresponding PD i bit reflects the value present on this pin If a port p...

Page 123: ... ESAI_2 and ESAI_3 are used by DSP Core 1 The only difference between ESAI and ESAI_2 is that ESAI ESAI_1 is used by DSP Core 0 and that ESAI_2 ESAI_3 is used by Core 1 There are no other differences This chapter describes the ESAI module The ESAI block diagram is shown in Figure 9 1 The ESAI is called synchronous because all serial transfers are synchronized to a clock Additional synchronization ...

Page 124: ...m SDO1 PC10 SDO0 PC11 Shift Register RX0 TX5 SDO5 SDI0 PC6 Shift Register RX1 TX4 SDO4 SDI1 PC7 Shift Register RX2 TX3 SDO3 SDI2 PC8 Shift Register RX3 TX2 SDO2 SDI3 PC9 Shift Register TX1 Shift Register TX0 DDB GDB RSMA RSMB TSMA TSMB RCCR RCR TCCR TCR SAICR SAISR TSR TCLK RCLK PC3 SCKT PC4 FST PC5 HCKT PC0 SCKR PC1 FSR PC2 HCKR Clock Frame Sync Generators and Control Logic ...

Page 125: ...O0 function is not being used 9 1 2 Serial Transmit 1 Data Pin SDO1 SDO1 is used for transmitting data from the TX1 serial transmit shift register SDO1 is an output when data is being transmitted from the TX1 shift register In the on demand mode with an internally generated bit clock the SDO1 pin becomes high impedance for a full clock period after the last data bit has been transmitted assuming a...

Page 126: ... shift register when programmed as a receiver pin SDO4 SDI1 is an input when data is being received by the RX1 shift register SDO4 SDI1 is an output when data is being transmitted from the TX4 shift register In the on demand mode with an internally generated bit clock the SDO4 SDI1 pin becomes high impedance for a full clock period after the last data bit has been transmitted assuming another data...

Page 127: ...alue at the pin is stored in the IF0 bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode SCKR may be programmed as a general purpose I O pin PC0 when the ESAI SCKR function is not being used NOTE Although the external ESAI serial clock can be independent of and asynchronous to the DSP system clock the DSP clock frequency must be at least four times t...

Page 128: ...ransmitter clock sources 1 0 1 1 1 EXTAL HCKR SCKR 1 1 0 0 0 SCKR HCKR FSR 1 1 0 0 1 SCKR HCKR FSR 1 1 0 1 0 SCKR HCKR FSR 1 1 0 1 1 SCKR HCKR FSR 1 1 1 0 0 Fsys HCKR FSR SCKR 1 1 1 0 1 Fsys HCKR FSR SCKR 1 1 1 1 0 EXTAL HCKR FSR SCKR 1 1 1 1 1 EXTAL HCKR FSR SCKR Table 9 2 Transmitter Clock Sources Asynchronous Mode Only THCKD TFSD TCKD ETI0 ETO0 Transmitter Bit Clock Source OUTPUTS 0 0 0 N A N A...

Page 129: ...mode SYN 1 it operates as either the serial flag 1 pin TEBE 0 or as the transmitter external buffer enable control TEBE 1 RFSD 1 For FSR pin mode definitions see Table 9 8 for receiver clock signals see Table 9 1 When this pin is configured as serial flag pin its direction is determined by the RFSD bit in the RCCR register When configured as the output flag OF1 this pin reflects the value of the O...

Page 130: ... is used as an alternative high frequency clock source to the ESAI transmitter rather than the DSP main clock When programmed as output it can serve as a high frequency sample clock to external DACs for example or as an additional system clock see Table 9 1 HCKT may be programmed as a general purpose I O pin PC5 when the ESAI HCKT function is not being used 9 1 12 High Frequency Clock for Receiver...

Page 131: ...ls the ESAI transmitter clock generator bit and frame sync rates the bit clock and high frequency clock sources and the directions of the HCKT FST and SCKT signals In the synchronous mode SYN 1 the bit clock defined for the transmitter determines the receiver bit clock as well TCCR also controls the number of words per frame for the serial data Hardware and software reset clear all the bits of the...

Page 132: ... Block Diagram FLAG0 OUT SYNC MODE FLAG0 IN SYNC MODE SCKR SCKT RCKD TCKD SYN 1 SYN 0 RCLOCK TCLOCK INTERNAL BIT CLOCK SYN 1 RSWS4 RSWS0 TSWS4 TSWS0 RX WORD LENGTH DIVIDER TX WORD LENGTH DIVIDER RX SHIFT REGISTER TX SHIFT REGISTER DIVIDE BY 2 PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 TPSR TPM0 TPM7 RX WORD CLOCK TX WORD CLOCK SYN 0 DIVIDE BY 2 PRESCALE DIVIDE BY 1 OR...

Page 133: ...and TFP3 TFP0 0 which causes synchronization problems when using the internal DSP clock as source TCKD 1 or THCKD 1 9 2 1 3 TCCR Tx Frame Rate Divider Control TDC4 TDC0 Bits 13 9 The TDC4 TDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the transmitter frame clocks In network mode this ratio may be interpreted as the number of words per frame minus one T...

Page 134: ...riven from an external high frequency clock the TFP3 TFP0 bits specify an additional division ratio in the clock divider chain Table 9 3 shows the specification for the divide ratio Figure 9 3 shows the ESAI high frequency clock generator functional diagram Table 9 3 Transmitter High Frequency Clock Divider TFP3 TFP0 Divide Ratio 0 1 1 2 2 3 3 4 F 16 FRAME SYNC TRANSMIT FRAME SYNC RECEIVE RX WORD ...

Page 135: ...nsmit high frequency bit clock and latched in on the falling edge of the transmit bit clock If THCKP is set the falling edge of the transmit clock is used to clock the data out and frame sync and the rising edge of the transmit clock is used to latch the data and frame sync in 9 2 1 8 TCCR Transmit Clock Source Direction TCKD Bit 21 The Transmitter Clock Source Direction TCKD bit selects the sourc...

Page 136: ...e can be the same as the normal mode or TE0 can be left enabled 9 2 2 2 TCR ESAI Transmit 1 Enable TE1 Bit 1 TE1 enables the transfer of data from TX1 to the transmit shift register 1 When TE1 is set and a frame sync is detected the transmit 1 portion of the ESAI is enabled for that frame When TE1 is cleared the transmitter 1 is disabled after completing transmission of data currently in the ESAI ...

Page 137: ...transfer of data from TX3 to the transmit shift register 3 When TE3 is set and a frame sync is detected the transmit 3 portion of the ESAI is enabled for that frame When TE3 is cleared the transmitter 3 is disabled after completing transmission of data currently in the ESAI transmit shift register Data can be written to TX3 when TE3 is cleared but the data is not transferred to the transmit shift ...

Page 138: ... If both RE0 and TE5 are cleared the transmitter and receiver are disabled and the pin is tri stated Both RE0 and TE5 should not be set at the same time The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx The normal transmit disable sequence is to clear TEx TIE and TEIE after TDE equals one In the network mode the operation of clearin...

Page 139: ... the word transfer rate one word is transferred per frame sync during the frame sync time slot as shown in Figure 9 6 In network mode it is possible to transfer a word for every time slot as shown in Figure 9 6 For further details see Section 9 3 Operating Modes To comply with AC 97 specifications TSWS4 TSWS0 should be set to 00011 20 bit slot 20 bit word length TFSL and TFSR should be cleared and...

Page 140: ... via the ESAI The word length must be equal to or shorter than the slot length The possible Normal Mode SERIAL CLOCK FRAME SYNC SERIAL DATA TRANSMITTER INTERRUPT OR DMA REQUEST AND FLAGS SET RECEIVER INTERRUPT OR DMA REQUEST AND FLAGS SET NOTE Interrupts occur and data is transferred once per frame sync Network Mode SERIAL CLOCK FRAME SYNC TRANSMITTER INTERRUPTS OR DMA REQUEST AND FLAGS SET SERIAL...

Page 141: ...ming model in Figure 9 13 and Figure 9 14 Table 9 5 ESAI Transmit Slot and Word Length Selection TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 SLOT LENGTH WORD LENGTH 0 0 0 0 0 8 8 0 0 1 0 0 12 8 0 0 0 0 1 12 0 1 0 0 0 16 8 0 0 1 0 1 12 0 0 0 1 0 16 0 1 1 0 0 20 8 0 1 0 0 1 12 0 0 1 1 0 16 0 0 0 1 1 20 1 0 0 0 0 24 8 0 1 1 0 1 12 0 1 0 1 0 16 0 0 1 1 1 20 1 1 1 1 0 24 1 1 0 0 0 32 8 1 0 1 0 1 12 1 0 0 1 0 16 0 1 ...

Page 142: ... to be generated or recognized If TFSL is cleared a word length frame sync is selected If TFSL is set a 1 bit clock period frame sync is selected See Figure 9 7 for examples of frame length selection 0 1 0 1 1 Reserved 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 Table 9 5 ESAI Transmit Slot and Word Length Selection Continued TSWS4 ...

Page 143: ... DATA NOTE Frame sync occurs while data is valid SERIAL CLOCK RX TX FRAME SYNC ONE BIT LENGTH TFSL 1 RFSL 1 RX TX SERIAL DATA NOTE Frame sync occurs for one bit time preceding the data SERIAL CLOCK TX FRAME SYNC MIXED FRAME LENGTH TFSL 1 RFSL 0 TX SERIAL DATA RX FRAME SYNC RX SERIAL DATA SERIAL CLOCK TX FRAME SYNC MIXED FRAME LENGTH TFSL 0 RFSL 1 TX SERIAL DATA RX FRAME SYNC RX SERIAL DATA DATA DA...

Page 144: ... and zero padding is disabled PADC 0 the first data bit is repeated before the transmission of the data word If zero padding is enabled PADC 1 zeroes are transmitted before the transmission of the data word 9 2 2 14 TCR Reserved Bit Bits 18 This bit is reserved It reads as zero and it should be written with zero for future compatibility 9 2 2 15 TCR Transmit Section Personal Reset TPR Bit 19 The T...

Page 145: ...pted when TIE and the TDE flag in the SAISR status register are set When TIE is cleared this interrupt is disabled Writing data to all the data registers of the enabled transmitters or to TSR clears TDE thus clearing the interrupt Transmit interrupts with exception have higher priority than normal transmit data interrupts therefore if exception occurs TUE is set and TEIE is set the ESAI requests a...

Page 146: ...quency is Fsys 4 the minimum internally generated bit clock frequency is Fsys 2 8 256 Fsys 4096 NOTE Do not use the combination RPSR 1 and RPM7 RPM0 00 which causes synchronization problems when using the internal DSP clock as source RHCKD 1 or RCKD 1 9 2 3 3 RCCR Rx Frame Rate Divider Control RDC4 RDC0 Bits 13 9 The RDC4 RDC0 bits control the divide ratio for the programmable frame rate dividers ...

Page 147: ...ck is used to latch the frame sync in 9 2 3 6 RCCR Receiver Frame Sync Polarity RFSP Bit 19 The Receiver Frame Sync Polarity RFSP determines the polarity of the receive frame sync signal When RFSP is cleared the frame sync signal polarity is positive that is the frame start is indicated by a high level on the frame sync pin When RFSP is set the frame sync signal polarity is negative that is the fr...

Page 148: ...he receiver frame sync signal when in the asynchronous mode SYN 0 and the IF1 OF1 Transmitter Buffer Enable flag direction in the synchronous mode SYN 1 In the asynchronous mode when RFSD is set the internal clock generator becomes the source of the receiver frame sync and is the output on the FSR pin In the asynchronous mode when RFSD is cleared the receiver frame sync source is external the inte...

Page 149: ...HCKD is set the HCKR pin becomes the OF2 output flag If RHCKD is cleared the HCKR pin becomes the IF2 input flag See Table 9 1 and Table 9 9 9 2 4 ESAI Receive Control Register RCR The read write Receive Control Register RCR controls the ESAI receiver section Interrupt enable bits for the receivers are provided in this control register The receivers are enabled in this register 0 1 2 or 3 receiver...

Page 150: ... 4 3 RCR ESAI Receiver 2 Enable RE2 Bit 2 When RE2 is set and TE3 is cleared the ESAI receiver 2 is enabled and samples data at the SDO3 SDI2 pin TX3 and RX2 should not be enabled at the same time RE2 1 and TE3 1 When RE2 is cleared receiver 2 is disabled by inhibiting data transfer into RX2 If this bit is cleared while receiving a data word the remainder of the word is shifted in and transferred ...

Page 151: ...e the frame rate divider determines the word transfer rate one word is transferred per frame sync during the frame sync time slot as shown in Figure 9 6 In network mode it is possible to transfer a word for every time slot as shown in Figure 9 6 For more details see Section 9 3 Operating Modes To comply with AC 97 specifications RSWS4 RSWS0 should be set to 00011 20 bit slot 20 bit word RFSL and R...

Page 152: ... 1 12 0 0 1 1 0 16 0 0 0 1 1 20 1 0 0 0 0 24 8 0 1 1 0 1 12 0 1 0 1 0 16 0 0 1 1 1 20 1 1 1 1 0 24 1 1 0 0 0 32 8 1 0 1 0 1 12 1 0 0 1 0 16 0 1 1 1 1 20 1 1 1 1 1 24 0 1 0 1 1 Reserved 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 Table 9 11 ESAI Receive Slot and Word Length Selection Continued RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 SLOT LENGT...

Page 153: ... to leave the personal reset state by clearing RPR the procedure described in Section 9 5 ESAI Initialization Examples should be followed 9 2 4 13 RCR Receive Exception Interrupt Enable REIE Bit 20 When REIE is set the DSP is interrupted when both RDF and ROE in the SAISR status register are set When REIE is cleared this interrupt is disabled Reading the SAISR status register followed by reading t...

Page 154: ...9 10 shows the ESAI Common Control register Hardware and software reset clear all the bits in the SAICR register 9 2 5 1 SAICR Serial Output Flag 0 OF0 Bit 0 The Serial Output Flag 0 OF0 is a data bit used to hold data to be send to the OF0 pin When the ESAI is in the synchronous clock mode SYN 1 the SCKR pin is configured as the ESAI flag 0 If the receiver serial clock direction bit RCKD is set t...

Page 155: ...ections use the transmitter section clock generator as the source of the clock and frame sync for both sections Also the receiver clock pins SCKR FSR and HCKR now operate as I O flags See Table 9 7 Table 9 8 and Table 9 9 for the effects of SYN on the receiver clock pins 9 2 5 6 SAICR Transmit External Buffer Enable TEBE Bit 7 The Transmitter External Buffer Enable TEBE bit controls the function o...

Page 156: ...ure 9 12 shows the ESAI Status register EXTERNAL FRAME SYNC FSR ASYNCHRONOUS SYN 0 TRANSMITTER CLOCK FRAME SYNC RECEIVER CLOCK FRAME SYNC SDI SDO FST EXTERNAL TRANSMIT FRAME SYNC EXTERNAL RECEIVE FRAME SYNC INTERNAL FRAME SYNC SCKR SCKT EXTERNAL TRANSMIT CLOCK EXTERNAL RECEIVE CLOCK INTERNAL CLOCK ESAI BIT CLOCK NOTE Transmitter and receiver may have different clocks and frame syncs SYNCHRONOUS SY...

Page 157: ...reception of the first received data bit after frame sync is detected The IF1 bit is updated with this data when the receiver shift registers are transferred into the receiver data registers IF1 reads as a zero when it is not enabled Hardware software ESAI individual and STOP reset clear IF1 9 2 6 3 SAISR Serial Input Flag 2 IF2 Bit 2 The IF2 bit is enabled only when the HCKR pin is defined as ESA...

Page 158: ...ansferred to the respective receive data register RDF is cleared when the DSP reads the receive data register of all enabled receivers or cleared by hardware software ESAI individual or STOP reset If RIE is set an ESAI receive data interrupt request is issued when RDF is set 9 2 6 8 SAISR Receive Even Data Register Full REDF Bit 9 When set REDF indicates that the received data in the receive data ...

Page 159: ...pty TDE Bit 15 TDE is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift registers it is also set for a TSR disabled time slot period in network mode as if data were being transmitted after the TSR was written When set TDE indicates that data should be written to all the TX registers of the enabled transmitters or to the time s...

Page 160: ...contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift registers it is also set for a TSR disabled time slot period in network mode as if data were being transmitted after the TSR was written When set TODE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register TSR TODE is cleared w...

Page 161: ... 32 bit mode is not shown 16 BIT 12 BIT 8 BIT SDO 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE ESAI TRANSMIT DATA REGISTER WRITE ONLY ESAI TRANSMIT SHIFT REGISTER 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE NOTES 1 Data is sent MSB first if TSHFD 0 2 24 bit fractional format ALC 0 3 32 bit mode is not shown 4 Data wor...

Page 162: ...IGNIFICANT ZERO FILL NOTES 1 Data is received LSB first if RSHFD 1 2 24 bit fractional format ALC 0 3 32 bit mode is not shown a Receive Registers SDO 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE ESAI TRANSMIT DATA REGISTER WRITE ONLY ESAI TRANSMIT SHIFT REGISTER 23 16 15 8 7 0 7 0 7 0 7 0 TRANSMIT HIGH BYTE TRANSMIT MIDDLE BYTE TRANSMIT LOW BYTE 24 BIT TSWS...

Page 163: ...of bits shifted out before the shift registers are considered empty and may be written to again can be 8 12 16 20 24 or 32 bits determined by the slot length control bits in the TCR register Data is shifted out of these registers MSB first if TSHFD 0 and LSB first if TSHFD 1 9 2 10 ESAI Transmit Data Registers TX5 TX4 TX3 TX2 TX1 TX0 TX5 TX4 TX3 TX2 TX1 and TX0 are 24 bit write only registers Data...

Page 164: ... slot When bit number N in TSM register is set the transmit sequence is as usual data is transferred from the TX registers to the shift registers and transmitted during slot number N and the TDE flag is set Using the slot mask in TSM does not conflict with using TSR Even if a slot is enabled in TSM the user may choose to write to TSR instead of writing to the transmit data registers TXx This cause...

Page 165: ...ters When bit number N in the RSM register is cleared the data from the enabled receivers input pins are shifted into their receive shift registers during slot number N The data is not transferred from the receive shift registers to the receive data registers and neither the RDF nor the ROE flag is set This means that during a disabled slot no receiver full interrupt is generated The DSP is interr...

Page 166: ... I O pins is programmed as an ESAI pin 9 3 2 ESAI Initialization The correct way to initialize the ESAI is as follows 1 Hardware software ESAI individual or STOP reset 2 Program ESAI control and time slot registers 3 Write data to all the enabled transmitters 4 Configure at least one pin as ESAI pin During program execution all ESAI pins may be defined as GPIO or disconnected causing the ESAI to s...

Page 167: ...ng data memory pointers Using the receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame is serviced with the new setting without synchronization problems Note that the maximum receive last slot interrupt service time should not exceed N 1 ESAI bits service time where N is the number of bits in a slot 5 ESAI Transmit Data with Except...

Page 168: ... channel devices Selecting the network mode and setting the frame rate divider to zero DC 00000 selects the on demand mode This special case does not generate a periodic frame sync A frame sync pulse is generated only when data is available to transmit The on demand mode requires that the transmit frame sync be internal output and the receive frame sync be external input Therefore for simplex oper...

Page 169: ...s word TFSR and RFSR are ignored when a bit length frame sync is selected Polarity of the frame sync signal may be defined as positive asserted high or negative asserted low The TFSP bit in the TCCR register specifies the polarity of the frame sync for the transmitter section The RFSP bit in the RCCR register specifies the polarity of the frame sync for the receiver section The ESAI receiver looks...

Page 170: ...ister respectively and they are driven when the transmit data registers are transferred to the transmit shift registers The value on SCKR FSR and HCKR is stable from the time the first bit of the transmit data word is transmitted until the first bit of the next transmit data word is transmitted Software may change the OF0 OF2 values thus controlling the SCKR FSR and HCKR pin values for each transm...

Page 171: ... PD i bit is reflected on this pin If a port pin i is configured as disconnected the corresponding PD i bit is not reset and contains undefined data Figure 9 21 shows the Port C Data register Table 9 12 PCRC and PRRC Bits Functionality PDC i PC i Port Pin i Function 0 0 disconnected 0 1 GPIO input 1 0 GPIO output 1 1 ESAI 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBF PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2...

Page 172: ...o be transmitted to the transmitters which are in use during operation This step is needed even if DMA is used to service the transmitters Enable the transmitters and receivers From now on ESAI can be serviced either by polling interrupts or DMA Operation proceeds as follows For internally generated clock and frame sync these signals are active immediately after ESAI is enabled step 3 above Data i...

Page 173: ...in set Take the receiver section out of the personal reset state by clearing RPR Enable the receivers by setting their RE bits From now on the receivers are operating and can be serviced either by polling interrupts or DMA 9 6 ESAI ESAI_2 and ESAI_1 ESAI_3 Pin Switch To support more flexible applications a pin switch between ESAI and ESAI_2 or ESAI_1 and ESAI_3 can be enabled Each pin of ESAI can ...

Page 174: ...r packages the clock and frame sync pins of ESAI_1 and ESAI_2 are not be bonded out while the clock and frame sync pins ESAI ESAI_3 are bonded out Using internal clock connection logic ESAI_1 can be connected to the ESAI pin out clocks and frame sync pins internally and also ESAI_2 can be connected to the ESAI_3 pin out clocks and frame sync pins internally For more information about this see Chap...

Page 175: ... modules SHI SHI_1 The only difference between SHI and SHI_1 is that SHI is used by DSP Core 0 and SHI_1 is used by DSP Core 1 Only SHI is described in detail in this chapter When configured in the SPI mode the SHI can perform the following functions Identify its slave selection in slave mode Simultaneously transmit shift out and receive shift in serial data Directly operate with 8 16 and 24 bit w...

Page 176: ...ructions and addressing modes In addition the MOVEP instruction allows interface to memory and memory to interface data transfers without going through an intermediate register The DMA controller can be used to service the receive or transmit data paths The single master configuration allows the DSP to directly connect to dumb peripheral devices for that purpose a programmable baud rate generator ...

Page 177: ...responsibility to select the proper clock rate within the correct range defined in the I2C and SPI bus specifications Figure 10 2 SHI Clock Generator 10 3 1 Serial Host Interface Programming Model The Serial Host Interface programming model has two parts a Host side and a DSP side Host side See Figure 10 3 and Section 10 3 2 SHI Input Output Shift Register IOSR Host Side DSP side See Figure 10 4 a...

Page 178: ...as 0 should be written with 0 for future compatibility HDM5 0 7 6 5 4 3 2 1 HDM6 HDM7 HDM2 HDM0 HDM1 HRS HDM3 HDM4 CPHA CPOL SHI Clock Control Register HCKR X FFFF90 0 23 HTX 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 HEN 0 7 6 5 4 3 2 1 HM1 HI 2 C HM0 HRQE0 HMST HRNE HBER HRFF HROE HBUSY HRQE1 HIDLE SHI Control Status Register HCSR HRIE0 HRIE1 HTUE HTDE HTIE X FFFF91 FIFO 10 Words Deep HBIE HF...

Page 179: ... significant byte of the IOSR is used as the shift register In 16 bit data transfer modes the two most significant bytes become the shift register In 24 bit transfer modes the shift register uses all three bytes of the IOSR NOTE The IOSR register cannot be accessed directly either by the host processor or by the DSP core The IOSR register is fully controlled by the SHI controller logic Table 10 1 ...

Page 180: ... data transfer mode all the contents of HTX register are transferred 10 3 4 SHI Host Receive Data FIFO HRX DSP Side The 24 bit host receive data FIFO HRX is a 10 word deep First In First Out FIFO register used for Host to DSP data transfers The serial data is received via the shift register and then loaded into the HRX FIFO In the different data transfer modes the following actions occur In 8 bit ...

Page 181: ...s HA 6 3 1011 and the HA1 bit is cleared this results in a default slave device address of 1011 HA2 0 HA0 10 3 7 SHI Clock Control Register HCKR DSP Side The HCKR register is a 24 bit read write register that controls the SHI clock generator The HCKR bits should be changed only while the SHI is in the individual reset state HEN 0 in the HCSR register For proper SHI clock set up please consult the ...

Page 182: ...clearing the HTDE bit However the data is transferred to the shift register for transmission only when the SS line is deasserted The HTDE bit is set when the data is transferred from the HTX register to the shift register When the SHI is in slave mode and CPHA bit 1 the SS line may remain asserted between successive word transfers Also the SS line must remain asserted between successive bytes with...

Page 183: ...of the HRS bit for the required serial clock frequency 10 3 7 3 HCKR Divider Modulus Select HDM 7 0 Bits 10 3 The HDM 7 0 bits specify the divide ratio of the clock generator divider A divide ratio between 1 and 256 HDM 7 0 00 to FF can be selected When the SHI operates in slave mode the HDM 7 0 bits are ignored except in HI2 C mode when the HCKFR bit is set The HDM 7 0 bits are cleared during har...

Page 184: ...HFM 1 0 are cleared during hardware reset and software reset After changing the filter bits in the HCKR register to a non bypass mode HFM 1 0 is not equal to 00 the programmer should wait at least ten times the tolerable spike width before enabling the SHI setting the HEN bit in the HCSR register Similarly after changing the HI2 C bit in the HCSR register or the CPOL bit in the HCKR register while...

Page 185: ...at an SHI individual reset be generated HEN bit cleared The HI2C bit is cleared during hardware and software resets 10 3 8 3 HCSR Serial Host Interface Mode HM 1 0 Bits 3 2 The read write control bits HM 1 0 select the size of the data words to be transferred as shown in Table 10 4 The HM 1 0 bits should be modified only when the SHI is idle HBUSY 0 The HM 1 0 bits are cleared during hardware and ...

Page 186: ...face operates in the master mode If the HMST bit is cleared then the SHI interface operates in the slave mode The SHI supports a single master configuration in both I2 C and SPI modes When configured as an SPI master the SHI drives the SCK line and controls the direction of the data lines using MOSI and MISO In SPI master mode the SS line must be held deasserted if the SS line is asserted when in ...

Page 187: ...a in the HTX register then a stop event is generated The HIDLE bit determines the acknowledge that the receiver sends after a byte is received correctly If the HIDLE bit is cleared then the byte s reception is acknowledged by sending a 0 bit on the SDA line at the ACK clock tick If the HIDLE bit is set then the byte s reception is not acknowledged a 1 bit is sent It is used to signal an end of dat...

Page 188: ...transmit interrupts are disabled and the HTDE status bit must be polled to determine if the HTX register is empty If both the HTIE and HTDE bits are set and the HTUE bit is cleared then the SHI requests an SHI transmit data interrupt service from the interrupt controller If both the HTIE and HTUE bits are set then the SHI requests an SHI transmit underrun error interrupt service from the interrupt...

Page 189: ...he shift register and the HTX register are empty and the external master begins reading the next word When operating in I2 C mode the HTUE bit is set on the falling edge of the ACK bit and the SHI re transmits the previously transmitted word When operating in SPI mode If CPHA 1 then the HTUE bit is set at the first clock edge If CPHA 0 then the HTUE bit is set at the assertion of the SS line If a ...

Page 190: ... when the HRX FIFO is read by the DSP using read instructions or DMA transfers reducing the number of words in the FIFO to zero The HRNE bit is cleared during hardware software and SHI individual resets and also during the stop state 10 3 8 16 Host Receive FIFO Full HRFF Bit 19 The read only status bit HRFF indicates when set that the Host Receive FIFO HRX is full The HRFF bit is cleared when the ...

Page 191: ...he SHI itself is busy when in the SPI mode When operating in I2 C mode the HBUSY bit is set after the SHI detects a start event and the HBUSY bit remains set until a stop event is detected When operating in the slave SPI mode the HBUSY bit is set while the SS line is asserted When operating in the master SPI mode the HBUSY bit is set if the HTX register is not empty or if the IOSR register is not ...

Page 192: ...bidirectional lines one for data signals SDA and one for clock signals SCL Both the SDA and SCL lines must be connected to a positive supply voltage via a pull up resistor NOTE In the I2C bus specifications the standard mode 100 kHz clock rate and a fast mode 400 kHz clock rate are defined The SHI can operate in either standard or fast mode 10 5 1 Overview The I2 C bus protocol must conform to the...

Page 193: ... low during the high period of the acknowledge related clock pulse see Figure 10 9 Figure 10 9 Acknowledgment on the I2 C Bus A device generating a signal is called a transmitter and a device receiving a signal is called a receiver A device controlling a signal is called a master and devices controlled by the master are called slaves A master receiver must signal an end of data to the slave transm...

Page 194: ...ure 10 11 Figure 10 10 I2 C Bus Protocol For Host Write Cycle Figure 10 11 I2C Bus Protocol For Host Read Cycle NOTE The first data byte in a write bus cycle can be used as a user predefined control byte for example to determine the location where the forthcoming data bytes should be transferred to 10 6 SHI Programming Considerations The SHI implements both SPI and I2 C bus protocols and can be pr...

Page 195: ...ed out via MISO and received data is shifted in via MOSI The DSP may write the HTX register using either DSP instructions or DMA transfers if the HTDE status bit is set If no writes to the HTX register occur the contents of the HTX register are not transferred to the IOSR register so the data shifted out when receiving is the data present in the IOSR register at that time The HRX FIFO contains val...

Page 196: ...y the interface performs simultaneous data receive and transmit The status bits of both receive and transmit paths are active however the programmer may disable undesired interrupts and ignore irrelevant status bits In a data transfer the HTX register is transferred to the IOSR register clock pulses are generated the IOSR register data is shifted out via MOSI and received data is shifted in via MI...

Page 197: ...ck pulse ACK 1 However the SHI controller continues to poll the SDA and SCL lines to detect a new start event If the slave device address byte was identified as its personal address if the personal slave device address was correctly identified then the slave device address byte is acknowledged ACK 0 is sent and a receive transmit session is initiated according to the 8th bit R W of the received sl...

Page 198: ... assuming the HTX register is not empty and the HTX register s contents are shifted out MSB first onto the SDA line Following each transmitted byte the SHI controller samples the SDA line at the 9th clock pulse and inspects the ACK status If the transmitted byte was acknowledged ACK 0 then the SHI controller continues and transmits the next byte However if the transmitted byte was not acknowledged...

Page 199: ...device address input HREQ is the Host Request input In the I2 C master mode a data transfer session is always initiated by the DSP by writing to the HTX register when the HIDLE bit is set This condition ensures that the data byte written to the HTX register is interpreted as being a slave address byte This data byte must specify the slave device address to be selected and the requested data transf...

Page 200: ...ber of bytes in an I2 C frame so that the bytes fit in a complete number of words For this purpose the slave device address byte does not count as part of the data the slave device address byte is treated separately If the I2 C slave transmitter is acknowledged it should transmit the next data byte To terminate the receive session the programmer should set the HIDLE bit at the last required data w...

Page 201: ...ata is written into the HTX register when the SHI proceeds with the transmit session or until the HIDLE bit is set the SHI re activates the clock to generate the stop event and terminate the transmit session 10 6 5 SHI Operation During DSP Stop The SHI operation cannot continue when the DSP is in the stop state because no DSP clocks are active While the DSP is in the stop state the SHI remains in ...

Page 202: ...SHI_1 blocks is in I2 C slave mode the other block must be in I2 C master mode or disabled If one of the SHI SHI_1 blocks is in I2 C master mode the other block must be disabled or in I2 C slave mode If both cores are in SPI slave mode When SHI SHI_1 is in SPI slave mode SS HA2 SS_1 HA2_1 is the SS SS_1 input In SPI slave mode the SS line should be kept asserted low during a data word transfer If ...

Page 203: ... function but only one of the SHI SHI_1 blocks at a time can control the output function of the HREQ pin NOTE Because both HREQ and HREQ_1 are function multiplexed with GPIO port H functions write the appropriate non contending values to the GPIO control registers before enabling the SHI function These constraints on SHI operations also apply to the boot modes of each core Care must be taken when ...

Page 204: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 10 30 Freescale Semiconductor Serial Host Interface SHI SHI_1 ...

Page 205: ...al purpose 24 bit timer event counters each with its own register set Each of the timers has the following capabilities Uses internal or external clocking Interrupts the DSP Core after a specified number of events clocks or signals an external device after counting internal events Triggers DMA transfers after a specified number of events clocks occurs 11 1 2 Triple Timer Module Block Diagram Figur...

Page 206: ...errupt programming techniques can be used to service the timers A single generic timer is discussed in this chapter Each timer includes the following 24 bit counter 24 bit read write Timer Control and Status Register TCSR 24 bit read only Timer Count Register TCR 24 bit write only Timer Load Register TLR 24 bit read write Timer Compare Register TCPR Logic for clock selection and interrupt DMA trig...

Page 207: ...for each timer A timer is active only if the timer enable bit 0 TCSR TE in the specific timer TCSR register is set 11 3 2 Timer Initialization To initialize a timer do the following 1 Ensure that the timer is not active either by sending a reset or by clearing the TCSR TE bit 2 Configure the control register TCSR to set the timer operating mode Set the interrupt enable bits as desired GDB Control ...

Page 208: ...eption configuration is complete 1 Configure the interrupt service routine ISR a Load vector base address register VBA b23 8 b Define I_VEC to be equal to the VBA value if that is nonzero If it is defined I_VEC must be defined for the assembler before the interrupt equate file is included c Load the exception vector table entry two word fast interrupt or jump branch to subroutine long interrupt p ...

Page 209: ...s set and a compare interrupt is generated if the TCSR TCIE bit is set If the TCSR TRM bit is set the counter is reloaded with the TLR register value at the next timer clock and the count is resumed If TCSR TRM is cleared the counter continues to increment on each timer clock signal This process repeats until the timer is disabled Figure 11 3 Timer Mode TRM 1 Table 11 1 Timer GPIO Mode 0 Bit Setti...

Page 210: ... are disconnected Any external changes that happen to the TIO signals are ignored when the corresponding DSP Core is in stop state To ensure correct operation disable the timers before the corresponding DSP Core is placed into stop state 11 4 4 DMA Trigger Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a timer event The timer issues a DMA trigger on eve...

Page 211: ...set and is using the prescaler output as its source that is one or more of the PCE bits are set Figure 11 5 Timer Module Programmer s Model DO DI DIR 15 14 13 12 11 10 9 8 TC1 TC0 INV TCIE TE 7 6 5 4 3 2 1 0 Timer Control Status Register TCSR Reserved bit Read as 0 Write with 0 for future compatibility 23 0 Timer Load Register TLR 23 22 21 20 19 18 17 16 23 0 Timer Compare Register TCPR PCE TRM TC...

Page 212: ...ed Write to zero for future compatibility 22 21 PS 1 0 0 Prescaler Source Controls the source of the prescaler clock The external clock is internally synchronized to the internal clock The external clock frequency must be lower than the DSP56725 internal operating frequency divided by 4 that is CLK 4 NOTE To ensure proper operation change the PS 1 0 bits only when the prescaler counter is disabled...

Page 213: ...14 PC13 PC12 11 10 9 8 7 6 5 4 3 2 1 0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Reserved bit read as 0 write to 0 for future compatibility Figure 11 7 Timer Prescaler Count Register TPCR Table 11 3 Timer Prescaler Count Register TPCR Bit Definitions Bit Name Reset Value Description 23 21 0 Reserved Write to zero for future compatibility 20 0 PC 20 0 0 Prescaler Counter Value Contain the c...

Page 214: ...red by a hardware RESET signal a software RESET instruction the STOP instruction or by clearing the TCSR TE bit to disable the timer 19 16 0 Reserved Write to zero for future compatibility 15 PCE 0 Prescaler Clock Enable Selects the prescaler clock as the timer source clock When the PCE bit is cleared the timer uses either an internal CLK 2 signal or an external TIO signal as its source clock When...

Page 215: ... 0 0 0 8 Reserved 1 0 0 1 9 Reserved 1 0 1 0 10 Reserved 1 0 1 1 11 Reserved 1 1 0 0 12 Reserved 1 1 0 1 13 Reserved 1 1 1 0 14 Reserved 1 1 1 1 15 Reserved Note The GPIO function is enabled only if all of the TC 3 0 bits are 0 3 0 Reserved Write to zero for future compatibility 2 TCIE 0 Timer Compare Interrupt Enable Enables disables the timer compare interrupts When set the TCIE bit enables the ...

Page 216: ...egister TCPR The TCPR is a 24 bit read write register that contains the value to be compared to the counter value These two values are compared every timer clock after TCSR TE is set When the values match the timer compare flag bit is set and an interrupt is generated if interrupts are enabled that is the timer compare interrupt enable bit in the TCSR register is set The TCPR register is ignored i...

Page 217: ...ut the WDT pin is asserted low after two EXTAL system clock cycle delays Following a reset of the device the WDT pin will de assert high after two EXTAL system clock cycle delays In the DSP56725 80 pin and 144 pin packages and the DSP56724 144 pin package the WDT and WDT_1 pins are ORed together so that when either watchdog timer times out the external pin is asserted The watchdog timer is driven ...

Page 218: ... down from the new value There are four registers in the WDT 1 The watchdog control register WCR configures the watchdog s operation 2 The watchdog modulus register WMR determines the timer modulus reload value 3 The watchdog count register WCNTR provides visibility to the counter value 4 The watchdog service register WSR requires a service sequence to prevent assertion of the WDT pin Figure 12 1 ...

Page 219: ...ed The WCR register is reset by a hardware reset only and the reset value is 00000F The WCR register can be updated in Debug mode and the WCR register retains the changed value after Debug mode If the WCR register has not been written before entering Debug mode then writing in Debug mode does not affect the WCR register s capability to be written once in Normal mode When Debug mode is exited the t...

Page 220: ... updated in the counter 3 Down counting The 16 bit counter is decremented every Fsys 4096 clock cycles When the counter value changes from 0000 to FFFF which means the WSR was not serviced properly the WDT pin is asserted The WDT pin assertion can only be cleared by hardware reset 12 3 3 Watchdog Modulus Register WMR The WMR register is a 16 bit read write register and is a write once register The...

Page 221: ...he value in the modulus register A hardware reset initializes the WMR register to 00FFFF 12 3 4 Watchdog Service Register WSR The WSR is a 16 bit write register and is used to service the Watchdog timer The WSR register is located at Y FFFFC3 When the watchdog timer is enabled the watchdog timer is serviced by writing 005555 and then writing 00AAAA to the watchdog service register WSR If the watch...

Page 222: ...CR 3 bit 12 4 2 Debug Mode If the WCR 1 bit is set the Watchdog timer function stops and enters Debug mode The counter and the prescaler retain their values during Debug mode If the WCR 1 bit is cleared the timer function is unaffected in Debug mode In Debug mode the WMR and WCR registers can be updated like a simple read write register The write once property of these registers do not apply in De...

Page 223: ...sters for inter core data exchange Figure 13 1 shows a block diagram of the ICC module 13 1 1 Overview The ICC block is interfaced to the peripheral bus of both DSP cores each core can access the registers that are dedicated to it This section describes all of the registers in the register block Figure 13 1 ICC Block Diagram ICC Maskable Interrupt Non Maskable Interrupt Error Interrupt Acknowledge...

Page 224: ...F_FFDB ICDR4 Y FF_FFD4 ICCR4 Y FF_FFD3 ICDR3 Y FF_FFD7 ICCR3 Y FF_FFD6 ICCR4 Y FF_FFD3 ICDR4 Y FF_FFD4 ICCR3 Y FF_FFD6 ICDR3 Y FF_FFD7 ICPR2 Y FF_FFD0 ICPR1 Y FF_FFD1 ICPR1 Y FF_FFD1 ICPR2 Y FF_FFD0 ICAR4 Y FF_FFD2 ICAR3 Y FF_FFD5 ICAR4 Y FF_FFD2 ICAR3 Y FF_FFD5 Core 1 Bus Non Maskable Inter Core Interrupts Inter Core Poll Registers Core 0 Bus Register Address Register Address Physical Registers M...

Page 225: ... data and status The contents of the polling register can be read by the other DSP core via its own read only polling register 13 2 Memory Map and Register Definition Table 13 1 shows the memory tables for ICC registers Each core has the same register address mapping 13 2 1 Memory Map Table 13 1 ICC Block Memory Map Offset or Address Register Access Reset Value Section Page y FFFFDB ICDR1 ICC Data...

Page 226: ...16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICDR1 Y FFFFDB R W Data R W Data ICCR1 Y FFFFDA R W R DRE IF W ICDR2 Y FFFFD9 R Data of the other Core s ICDR1 register W R Data of the other Core s ICDR1 register W ICCR2 Y FFFFD8 R W R DRE IF W ICDR3 Y FFFFD7 R W Data R W Data ICCR3 Y FFFFD6 R W R EIE EF MIF MIE W ICAR3 Y FFFFD5 R W R RACK ACK W ICDR4 Y FFFFD4 R Data of the other Core s ICDR3 register W R...

Page 227: ... W R RACK ACK W ICPR1 Y FFFFD1 R Poll data from the other Core s ICPR2 register W R Poll data from the other Core s ICPR2 register W ICPR2 Y FFFFD0 R Poll Data to the other core ICPR2 Data W R Poll Data to the other core ICPR2 Data W Address Y FFFFDB Access User Write 23 22 21 20 19 18 17 16 15 14 13 12 R W Communication Data Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R W Communicatio...

Page 228: ...ites this register to issue a non maskable Interrupt to the other core Address Y FFFFDA Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R DRE IF W Reset 0 0 0 0 0 0 0 0 0 1 0 0 Figure 13 4 ICCR1 Control Register 1 Table 13 4 ICCR1 Field Descriptions Bit Field Description 23 3 Reserved Read only 2 DRE Data Register Empty Read only res...

Page 229: ...unication Data Read only communication data reflecting the other core s ICDR1 data register Address Y FFFFD8 Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R DRE IF W Reset 0 0 0 0 0 0 0 0 0 1 0 0 Figure 13 6 ICCR2 Control Register Table 13 6 ICCR2 Field Descriptions Bit Field Description 23 3 Reserved Read only 2 DRE Data Register ...

Page 230: ...cation Data Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13 7 ICDR3 Data Register Table 13 7 ICDR3 Field Descriptions Bit Field Description 23 0 Communication Data Communication data that written by one core to issue a Maskable Interrupt to the other core Address Y FFFFD6 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R EIE EF MIF MIE...

Page 231: ...pt condition occurs 0 Interrupt Disabled No interrupt will be generated even if the interrupt condition occurs Address Y FFFFD5 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R RACK ACK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13 9 ICC ICAR3 Control Register Table 13 9 ICAR3 Field Descriptions Bit Field Description 23 2 Reserved...

Page 232: ... Data Register Table 13 10 ICDR4 Field Descriptions Bit Field Description 23 0 Communication Data Read only communication data that reflects the other core s ICDR3 data register Address Y FFFFD3 Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R EIE EF MIF MIE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13 11 ICCR4 Control Register Table 1...

Page 233: ...e bit of the other core s ICCR3 register 1 Interrupt is Enabled 0 Interrupt is Disabled Address Y FFFFD2 Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R RACK ACK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13 12 ICAR4 Control Register Table 13 12 ICAR4 Field Descriptions Bit Field Description 23 2 Reserved Write 0 to ensure future compa...

Page 234: ...Data W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13 13 ICC_ICPR1 Polling Register Table 13 13 CPR1 Field Descriptions Bit Field Description 23 0 Poll Data 24 bit Poll data from the other core Read Only Address Y FFFFD0 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 R Data W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R Data W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13 14 ICPR2 Poll...

Page 235: ...vice routine to clear the interrupt The priority of the interrupt is determined by the corresponding bits in the PIC register IPRP 13 3 1 Inter Core Maskable Interrupts The maskable interrupt operation is shown in Figure 13 15 Figure 13 15 Maskable Interrupts In Figure 13 15 the 24 bit data register is used to store the maskable interrupt communication data that will be read out by the other core ...

Page 236: ...own in Figure 13 16 Figure 13 16 Non Maskable Interrupts When one DSP core needs to generate a non maskable interrupt to the other core that core writes a datum to the ICDR1 data register However the data can be written to this register and the IF bit can only be set when DRE is 1 which indicates that the data register is empty So the DRE bit must be polled before writing a datum to the ICDR1 data...

Page 237: ...error interrupt This situation will not happen if reading the ICDR4 register is always executed in the maskable interrupt service routine Generating this error interrupt condition is only for handling such an error in case that the wrong operation takes place For the communications via maskable interrupt users should always read the ICDR4 register in the maskable interrupt service routine Figure 1...

Page 238: ...s this error interrupt you must poll this ESIR register in the interrupt service routine If the interrupt is caused by the ICC then write a one 1 to the ICCR3 2 bit to clear this status flag 13 3 5 Reset Both hardware reset and software reset can put all of the ICC registers to a known state Address Y FFFFC8 Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 ...

Page 239: ...rbiter 14 1 2 Features Each Shared Bus is a multiplexed bus of the DSP core s P X and Y buses and the DMA bus Arbitration on each Shared Bus between the DSP core and its DMA is configured by the Core DMA Priority bits in the OMR register see Chapter 5 Core Configuration for more information This section is limited to describing the arbitration between the shared bus for Core 0 DMA 0 and the shared...

Page 240: ... When Shared Bus access contention occurs the Arbiter Control Register ARCR in the chip configuration module determines the arbitration method Three static arbitration methods are supported Shared Bus Master 0 always has priority Shared Bus Master 1 always has priority and the round robin method the bus masters take turns getting bus access See the Chapter 20 Chip Configuration Module for more abo...

Page 241: ...r Out M0 1 M0 2 M0 3 M0 4 M1 2 M1 3 M1 4 M1 5 M1 1 M0 1 M0 2 M0 3 M0 4 M1 1 M1 2 M1 3 M1 4 M1 5 Master 0 Master 1 Note All accesses are assumed to finish with 0 wait states after the arbitration has occurred System Clock Master 0 Req Master 0 Access Master 1 Req Master 1 Access Arbiter Out M0 1 M0 2 M0 3 M0 4 M0 5 M1 1 M1 2 M1 3 M1 4 M0 1 M0 2 M0 3 M0 4 M0 5 M1 1 M1 2 M1 3 M1 4 Master 0 Master 1 N...

Page 242: ...ernating between the two bus masters All it takes is one access from either Master 0 or Master 1 with no contention and bus access goes back to Master 0 first on the next bus contention Table 14 1 Round Robin Arbitration Method State Input Output Flag Master 0 Master 1 Master 0 Master 1 Flag 1 0 0 0 0 0 0 2 0 0 1 0 1 0 3 0 1 0 1 0 0 4 0 1 1 1 0 1 5 1 0 0 N A 6 1 0 1 0 1 0 7 1 1 0 N A 8 1 1 1 0 1 0...

Page 243: ...s access can be set by configuring the corresponding DMA channel control register If a DMA continuous access has priority over the other Shared Bus master then the Shared Bus master must wait until one cycle after the DMA continuous access has completed before it takes the access For shared memory access DMA continuous access is ignored the core RMW instruction is not ignored If DMA uses continuou...

Page 244: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 14 6 Freescale Semiconductor Shared Bus Arbiter ...

Page 245: ...ntion 15 2 Block Diagram To reduce access conflict the entire shared memory space is divided into several shared memory banks Shared Bus 0 and Shared Bus 1 accesses are able to happen simultaneously as long as the two accesses do not hit the same memory bank If both Cores or DMA attempt to access data within the same shared memory block a delay of at least 1 cycle will occur but no data will be lo...

Page 246: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 15 2 Freescale Semiconductor Shared Memory Shared Memory ...

Page 247: ...ure 16 1 shows how the Shared Peripheral Bus fits into the DSP56724 DSP56725 device Figure 16 1 Shared Peripheral Bus in DSP56724 DSP56725 16 1 1 Features Shared Peripheral Bus features include Two arbitration methods are used Fixed arbitration Round robin arbitration Specific arbitration methods for continuous transfers for DSP Cores and DMAs Fire and forget single write accesses No additional de...

Page 248: ... states but the Shared Peripheral Bus will still take the required number of wait states to complete the bus access This has the effect of adding wait states to any subsequent accesses during that time Read accesses on the Shared Peripheral Bus usually complete with zero wait states in addition to any wait states added by the particular peripheral accessed and the Shared Bus arbitration However an...

Page 249: ...OTE The EMC is not available on the DSP56725 device 17 1 Introduction The EMC Burst Buffer converts single transactions on the Shared Bus to EMC burst transactions Figure 17 1 shows how the EMC Burst Buffer is incorporated in the DSP56724 device In the DSP56724 Core 0 DMA 0 is Shared Bus master 0 and Core 1 DMA 1 is Shared Bus master 1 ...

Page 250: ...ite respectively Each burst buffer has 16 24 bit words alternating ping pong style between the two sets of 8 words Core 0 External Memory EMC BAR Reg 0 Reg 1 Reg 2 Reg 3 Reg 4 Reg 5 Reg 6 Reg 7 Read Buffer 0 BAR Base Address Register Reg 24 bit Register DMA 0 Core DMA Arbiter Shared Bus Arbiter Core 1 DMA 1 Core DMA Arbiter Shared Bus BAR Reg 0 Reg 1 Reg 2 Reg 3 Reg 4 Reg 5 Reg 6 Reg 7 BAR Reg 0 R...

Page 251: ... also finish with zero wait states Four burst buffers are included in the burst cache of the gasket for Shared Bus master 0 read Shared Bus master 0 write Shared Bus master 1 read and Shared Bus master 1 write respectively Each buffer has 16 24 bit words alternating ping pong operation between the two sets of 8 Burst operation can be controlled by configuring the corresponding register bits in the...

Page 252: ...emory and will stall access requests from any Shared Bus master 0 1 until all of the data in the burst buffer is written to external memory After invalidation of the write buffer has finished the hardware automatically clears the corresponding register bit IWB0 or IWB1 Table 17 1 External Memory X Space Burst Control EXMBC Action 00 Module doesn t burst any external memory accesses inside the X ad...

Page 253: ...3 2 1 Single Read For single read access the EMC Burst Buffer passes the access straight through to the EMC without any other functions being involved Yes No 1st 8 word buffer is hit No Yes 2nd 8 word buffer is hit No 1st hit refreshed after this 8 word Buffer Return the hit data and begin 8 beat burst read on 2nd 8 word buffer Return the hit data and begin 8 beat burst read on 1st 8 word buffer 1...

Page 254: ...ffer and the buffer returns the read data to the Shared Bus directly with zero wait states If no 8 word buffer is hit the module sends an 8 word burst request to the EMC to load 8 words from external memory into the first 8 word buffer at the same time the access address is loaded into the base address register After the burst operation has finished the corresponding valid bit is set and the read ...

Page 255: ...to the EMC The EMC Burst Buffer will stall any following request acknowledge accesses from the Shared Bus until the EMC is ready for the next access Current 8 word buffer Yes Yes No Sequential address Store write data into the No No Yes Begin burst write on the data in this 8 word buffer and set the other 8 word buffer to be the current 8 word buffer current 8 word buffer empty Is there burst writ...

Page 256: ...8 word buffer stores the write data in it terminates the access immediately without involving the EMC and returns the address of the first write data is stored into the base address register If the 8 word buffer is not empty and is not a sequential address the sub buffer stores the write data left in it into external memory through the EMC by executing a burst operation the burst length is the num...

Page 257: ...nal components in the system such as the on chip S PDIF transmitter ESAI ports as well as external A Ds or D As with clocking control provided via related registers Figure 18 1 shows a block diagram of the S PDIF transceiver data paths receiver and transmitter and its interface Figure 18 1 S PDIF Transceiver Data Interface Block Diagram SPDIFOUT1 SELECT SPDIFOUT2 S PDIF Receiver S PDIF RCV FIFO Le...

Page 258: ...at IEC958 which consists of audio data channel status and user bits In the S PDIF transmitter the IEC958 biphase bit stream is generated on both edges of the S PDIF Transmit clock The S PDIF Transmit clock is generated by the S PDIF internal clock generate module and the sources are from outside of the S PDIF block For the S PDIF receiver it can recover the S PDIF rcv clock Both the tx clock and r...

Page 259: ...Signal Type State during Reset Description SPDIFIN1 Input GPIO Disconnected S PDIF Input Line 1 IEC958 data in biphase mark format SPDIFIN2 Input GPIO Disconnected S PDIF Input Line 2 IEC958 data in biphase mark format SPDIFIN3 Input GPIO Disconnected S PDIF Input line 3 IEC958 data in biphase mark format SPDIFIN4 Input GPIO Disconnected S PDIF Input Line 4 IEC958 data in biphase mark format SPDIF...

Page 260: ...x000000 X FFFF67 R SPDIFRcvCChannel_h SRCSH S PDIF Receive C channel bits 47 24 24 23 0 0x000000 X FFFF68 R SPDIFRcvCChannel_l SRCSL S PDIF Receive C channel bits 23 0 24 23 0 0x000000 X FFFF69 R UchannelRcv SQU S PDIF Receive U channel 24 23 0 0x000000 X FFFF6A R QchannelRcv SRQ S PDIF Receive Q channel 24 23 0 0x000000 X FFFF6B W SPDIFTxLeft STL S PDIF Transmit Left channel 24 23 0 0x000000 X FF...

Page 261: ...ription 23 RcvFifo_Ctrl 0 Normal operation 1 Always read zero from rcv data register 22 RcvFifo_Off On 0 S PDIF Rcv FIFO is on 1 S PDIF Rcv FIFO is off Does not accept data from interface 21 RcvFifo_Rst 0 Normal operation 1 Reset register to 1 sample remaining 20 19 RcvFifoFull_Sel 00 Full interrupt if at least 1 sample in FIFO 01 Full interrupt if at least 2 sample in FIFO 10 Full interrupt if at...

Page 262: ...Channel Source Select 00 No embedded U channel 01 U channel from S PDIF receive block CD mode 10 Reserved 11 U channel from on chip transmitter Address X FFFF61 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 R 9 b0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R 5 b0 USyncMode W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 4 CDText Control Register SRCD Table 18 4 CDText Control...

Page 263: ...0 9 8 7 6 5 4 3 2 1 0 R 1 b0 ClkSrc_Sel LOCK GainSel 3 b0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 5 PhaseConfig Register SRPC Table 18 5 PhaseConfig Register SRPC Field Descriptions Bit Field Description 23 11 Reserved Return zeros when read 10 7 ClkSrc_Sel Clock source selection 0000 if DPLL Locked SPDIF_RcvClk else EXTAL 0001 if DPLL Locked SPDIF_RcvClk else HCKT 0010 if DPLL Locked SPDIF_RcvC...

Page 264: ...0 0 0 0 0 0 0 Figure 18 6 InterruptEn Register SIE Address X FFFF64 Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 R 3 b0 Lock TxUnOv TxResyn CNew ValNoGood SymErr BitErr 2 b0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R 1 b0 URxFul URxOv QRxFul QRxOv UQSync UQErr PdirUnOv PdirResyn LockLoss TxEm PdirFul W Reset 0 0 0 0 0 0 0 0 0 0 1 0 Figure 18 7 InterruptStat Register SIS Ad...

Page 265: ... PDIF receiver found illegal symbol 14 BitErr S PDIF receiver found parity bit error 13 11 Reserved Return zeros when read 10 URxFul UChannel receive register is full The URxFul bit can t be cleared using the IntClear register To clear the URxFul bit read from U RCV register 9 URxOv UChannel receive register is overrun 8 QRxFul QChannel receive register is full The QRxFul bit can t be cleared usin...

Page 266: ...2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RcvDataRight W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 10 SPDIFRcvRight Register SRR Table 18 8 SPDIFRcvRight Register SRR Fields Bit Field Description 23 0 RcvDataRight Processor receives S PDIF data right Address X FFFF67 Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RxCChannel_...

Page 267: ...ister Contains the next 24 bits of C channel without interpretation Address X FFFF69 Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RxUChannel W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 13 S PDIF UchannelRcv Register SRU Table 18 11 S PDIF UchannelRcv Register SRU Fields Bit Field Description 23 0 RxUChannel S PDIF receive U channel register...

Page 268: ...ead Address X FFFF6C Access User Write 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 24 b0 W TxDataRight Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 16 SPDIFTxRight Register STR Table 18 14 SPDIFTxRight Register STR Fields Bit Field Description 23 0 TxDataRight S PDIF transmit right channel data It is write only and always returns zeros when read Address X FFF...

Page 269: ... 6 5 4 3 2 1 0 R TxCChannelProf_h W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 19 SPDIFTxChannelProf_h Register STCSPH Table 18 17 SPDIFTxChannelProf_h Register STCSPH Fields Bit Field Description 23 8 Reserved Returns zeros when read 7 0 TxCChannelProf_h S PDIF transmit professional C channel data Contains the first 8 bits without interpretation When read it returns the lates...

Page 270: ...FM Table 18 19 S PDIF FreqMeas Register SRFM Fields Bit Field Description 23 0 FreqMeas Frequency measurement Address X FFFF74 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 4 b0 SYSCLK_DF TxClk_Source 0 TxClk_DF W Reset 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Figure 18 22 SPDIFTxClk Register STC Table 18 20 SPDIFTxClk Register STC Fields Bit Field D...

Page 271: ...Status bits Reception see Section 18 3 2 Channel Status Reception User Channel bits Reception see Section 18 3 3 User Bit Reception Validity Flag Reception see Section 18 3 4 Validity Flag Reception S PDIF Receiver Exception support see Section 18 3 5 S PDIF Receiver Interrupt Exception Definition S PDIF Lock Detection 18 3 1 Audio Data Reception The S PDIF Receiver block extracts the audio data f...

Page 272: ...a state machine with 3 states OFF STANDBY and ON In the ON state the filling of the left FIFO is compared with the filling of right FIFO and if they are not equal the right FIFO is made equal to the left FIFO and an interrupt is generated The controller will stay in the OFF state when the automatic FIFO resynchronization feature is disabled When the automatic FIFO resynchronization feature is not ...

Page 273: ...r the software To read the first 6 samples from the LEFT address followed by 6 samples from the RIGHT address Or to read 6 samples from the RIGHT address followed by 6 samples from the LEFT address Or to read 1 sample LEFT followed by 1 sample RIGHT repeated 6 times There is no order specified The implementation for SPDIFRcv is a double FIFO with one FIFO for left and one FIFO for right Full is se...

Page 274: ...in S PDIF receiver This mode is selected if UsyncMode bit 1 in the CDText control register is set to 1 The CD subcode stream embedded into the S PDIF User channel consists of a sequence of packets Every packet is made up of 98 symbols The first two symbols of every packet are sync symbols while the other 96 symbols are data symbols Any sequence found in the S PDIF U channel stream starting with a ...

Page 275: ...nsfer this data 4 QChannelRcvFull interrupts are generated When a QChannelRcvFull interrupt occurs it is coincident with a UChannelRcvFull interrupt There is only one QChannelRcvFull interrupt for every 8 UChannelRcvFull interrupts The convention is that the most significant data is transmitted first and is left aligned in the registers Timing regarding the packet boundary is extracted by hardware...

Page 276: ...l is left aligned the last symbol is right aligned When the UchannelRcv register contains 3 new data symbols the UChannelRcvFull interrupt is asserted In this mode the operation of QchannelRcv and associated interrupt QchannelRcvFull is Reserved Undefined Also Reserved Undefined is the operation of UQFrameError and UQSyncFound The U channel is extracted and output by the S PDIF Rcv block on SPDIFR...

Page 277: ...and split it in so called symbols It recognizes s1 s2 and s3 symbols depending on the length of the symbols Not all sequences of these symbols are allowed For example a sequence s2 s1 s1 s1 s2 cannot occur in a no error S PDIF signal If the receiver finds such an illegal sequence the illegal symbol interrupt is set No corrective action is undertaken When the interrupt occurs this means that a The ...

Page 278: ... clock the internal DPLL can extract the bit clock advanced pulse from the input bitstream When this internal DPLL is locked the LOCK bit of PhaseConfig Register will be set and the S PDIF Lock output pin SPLOCK will be asserted After DPLL has locked the pulses are generated and the average pulse rate is 128 x the sampling frequency For a 44 1 Khz input sampling frequency the average pulse rate 12...

Page 279: ...tween the FIFOs If the S PDIF Tx FIFO underruns for example on the right half of the FIFO no sample leaves that FIFO because it was already empty Special hardware will make sure that the next sample read from the left FIFO will not leave the FIFO no read strobe will be generated If the underrun occurs on the left half of the FIFO then the next read strobe to the right FIFO is blocked b S PDIF Tran...

Page 280: ... A total of 48 Consumer channel status bits are transmitted from two registers Channel Status Bits are ordered first bit left CS channel MSB bit 0 is located in bit position 23 in the memory mapped register SPDIFTxCChannelCons_h CS channel bit 23 is considered bit 0 in the register C channel bits 24 47 are seen as MSB LSB bits of register SPDIFTxCChannelCons_l A total of 32 Professional channel st...

Page 281: ...w the ASRC module connects to other modules Figure 19 1 ASRC Connections DSP Platform Peripheral Bus S PDIF ESAI Rx clock ESAI 1 Rx clock ESAI Tx clock ESAI 1 Tx clock ESAI 2 Rx clock ESAI 3 Rx clock ESAI 2 Tx clock ESAI 3 Tx clock DMA reqs Interrupt requests and vectors for Core 0 SS PDIFPDIF Tx ASRCKl ESAI ESAI 1 ESAI 2 ESAI 3 S PDIF Rx Clock Interrupt requests and vectors for Core 1 ASRC ...

Page 282: ...verter ASRC converts the sampling rate of a signal associated with an input clock into a signal associated to a different output clock The ASRC supports concurrent sample rate conversion of up to 10 channels at about 120 dB THD N The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates The ASRC supports up to 3 sampling rate pairs The ASRC is hard ...

Page 283: ...itter Clock Data Connections The physical sampling clocks are directly connected to the ASRC module and the ratio estimation of the input clocks with output clocks are done in ASRC hardware when both the input and output sampling clocks are physically available When this is the case the rate conversion can be done by configuring the physical clocks When the input clock is not physically available ...

Page 284: ...reshold ASRC will set ASRSTR_AIDEx x A B or C After DSP checks the ASRSTR and finds these input requests the DSP will write enough data into the ASRDIA ASRDIB or ASRDIC input register accordingly before the ASRC fetches the next data When the ASRC fetches the next data and if the FIFOs are empty an error will happen and ASRSTR_AOLE will be set The threshold of the input FIFOs is 32 samples by defa...

Page 285: ... is almost the same as input mode 1 except that the direction of data being transferred and the involved register bits are different The threshold of the output FIFOs is 32 samples the FIFO size of each channel is 64 samples Mode 2 Interrupt Mode Output mode 2 is also an interrupt mode It is almost the same as input mode 2 except that again the direction of data being transferred and the involved ...

Page 286: ...Task queue FIFO Register 1 R W2 0x00_0000 19 2 2 11 19 25 0x16 Reserved 0x17 ASRCCR Channel Counter Register R W 0x00_0000 19 2 2 12 19 26 0x18 ASRDIA ASRC Data Input Register for Pair A W NA3 19 2 2 13 19 26 0x19 ASRDOA ASRC Data Output Register for Pair A R NA4 19 2 2 13 19 26 0x1A ASRDIB ASRC Data Input Register for Pair B W NA5 19 2 2 13 19 26 0x1B ASRDOB ASRC Data Output Register for Pair B R...

Page 287: ...n the read or write row indicates that the bit is not readable or not writeable FIELDNAME Identifies the field Its presence in the read or write row indicates that it can be read or written Register Field Types R Read only Writing this bit has no effect W Write only R W Standard read write bit Only software can change the bit s value other than a hardware reset rwm A read write bit that may be mod...

Page 288: ...en the ATSB bit is 1 pair B will automatic update its pre processing and post processing options ASRCFG PREMODB ASRCFG POSTMODB see Section 19 2 2 4 Filter Configuration Status Register ASRCFG based on the frequencies it detected To use this option the two parameter registers TS76KHZ and TS56KHZ should be set correctly through the ASRMAA and ASRMAD registers see Section 19 2 2 9 Memory Access Regi...

Page 289: ...gure 19 6 Interrupt Enable Mask Register ASRIEM 1 ASREA ASRC Enable A Enables the conversion of pair A of the ASRC When ASREA is cleared conversion of pair A is disabled 0 ASRCEN ASRC Enable Enables the operation of the ASRC Offset 0x1 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R AFPWE AOLIE ADOEC ADOEB ADOEA ADIEC ADIEB A...

Page 290: ...t Enable Enables the data input A Interrupt Table 19 6 Interrupt Enable Mask Register ASRIEM Bit Field Description 23 8 Reserved Should be written as zero for compatibility 7 MFPWE Mask of FP in Wait State Interrupt 0 Enables the wait state interrupt to Core 1 1 Enables the wait state interrupt to Core 2 6 MOLIE Mask of Overload Interrupt Enable 0 Enables the overload interrupt to Core 1 1 Enables...

Page 291: ...ta input B interrupt to Core 2 0 MDIEA Mask of Data Input A Interrupt Enable 0 Enables the data input A Interrupt to Core 1 1 Enables the data input A Interrupt to Core 2 Offset 0x3 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R ANCC ANCB ANCA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 7 Channel Number Configuration Register A...

Page 292: ...air B is disabled 001 2 channel in B 010 4 channels in B 011 6 channels in B 100 8 channels in B 101 10 channels in B 2 0 ANCA Number of A Channels 000 0 channels in A Pair A is disabled 001 2 channel in A 010 4 channels in A 011 6 channels in A 100 8 channels in A 101 10 channels in A 1 ANCC ANCB ANCA 10 Offset 0x4 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 R INIRQC INIRQB INIRQA ...

Page 293: ...7 16 POSTMODC 1 0 Post Processing Configuration for Conversion Pair C Use these bits to set the selection of the post processing configuration for Pair C 00 Select Upsampling by 2 as defined in Section 19 5 1 1 Signal Processing Flow 01 Select Direct Connection as defined in Section 19 5 1 1 Signal Processing Flow 10 Select Downsampling by 2 as defined in Section 19 5 1 1 Signal Processing Flow Th...

Page 294: ...d in Section 19 5 1 1 Signal Processing Flow 01 Select Direct Connection as defined in Section 19 5 1 1 Signal Processing Flow 10 Select Downsampling by 2 as defined in Section 19 5 1 1 Signal Processing Flow These bits can be read written by the user if ASRCTR ATSA 0 and can also be automatically updated by the ASRC internal logic if ASRCTR ATSA 1 see Table 19 4 7 6 PREMODA 1 0 Pre Processing Con...

Page 295: ...00 S PDIF Tx clock 0101 Reserved 0110 Reserved 0111 Reserved Any other value ASRCK1 In DSP56724 DSP56725 this signal is derived from the PLL and can be controlled by the ASCDR register in the CGM module 15 12 AOCSA Output Clock Source A 0000 ESAI Tx clock 0001 ESAI 1 Tx clock 0010 ESAI 2 Tx clock 0011 ESAI 3 Tx clock 0100 S PDIF Tx clock 0101 Reserved 0110 Reserved 0111 Reserved Any other value AS...

Page 296: ...Reserved Any other value ASRCK1 In DSP56724 DSP56725 this signal is derived from the PLL and can be controlled by the ASCDR register in the CGM module 3 0 AICSA Input Clock Source A 0000 ESAI Rx clock 0001 ESAI 1 Rx clock 0010 ESAI 2 Rx clock 0011 ESAI 3 Rx clock 0100 S PDIF Rx clock 0101 Reserved 0110 Reserved Any other value ASRCK1 In DSP56724 DSP56725 this signal is derived from the PLL and can...

Page 297: ...power of 2 from 1 to 128 17 15 AOCDA Output Clock Divider A Specify the divide ratio of the output clock divider A The divide ratio can be from 1 to 8 AOCDA 2 0 000 to 111 14 12 AOCPA Output Clock Prescaler A Specify the prescaling factor of the output prescaler A The prescaling ratio may be any power of 2 from 1 to 128 11 9 AICDB Input Clock Divider B Specify the divide ratio of the input clock d...

Page 298: ...cify the divide ratio of the input clock divider C The divide ratio is from 1 to 8 AICDC 2 0 000 to 111 2 0 AICPC Input Clock Prescaler C Specify the prescaling factor of the input prescaler C The prescaling ratio may be any power of 2 from 1 to 128 Offset 0x8 Access User Read Only 23 22 21 20 19 18 17 16 15 14 13 12 R DSLCNT ATQOL AOOLC AOOLB AOOLA AIOLC AIOLB AIOLA AODOC AODOB W Reset 0 0 0 0 0 ...

Page 299: ...B Input Task Overload 1 Indicates that the pair B input task is oveloaded This may help to check the reason why overload interrupt happens The AIOLB bit is cleared when writing 1 to ASRCTR AOLIE 14 AIOLA Pair A Input Task Overload 1 Indicates that the pair A input task is oveloaded This may help to check the reason why overload interrupt happens The AIOLA bit is cleared when writing 1 to ASRCTR AO...

Page 300: ...ys generated when the AODFC bit is set but a DMA transfer takes place only if a DMA channel is active and triggered by this event 4 AODFB Number of data in Output Data Buffer B is greater than threshold 1 Indicates that the number of data words already existing in ASRDORB is greater than the threshold and the DSP can read data from ASRDORB When AODFB is set the ASRC generates a data output B inter...

Page 301: ...B bit is set but a DMA transfer takes place only if a DMA channel is active and triggered by this event 0 AIDEA Number of data in Input Data Buffer A is less than threshold 1 Indicates that the number of data words still available in ASRDIRA is less than the threshold and the DSP can write data to ASRDIRA When AIDEA is set the ASRC generates a data input A interrupt request to the DSP core if enab...

Page 302: ...t the task queue is not empty In debug mode it is not recommended to generate new tasks when this bit is 1 b0 16 12 PFWPT 4 0 Write Pointer for Prefilter Output Buffer This is the write pointer for the prefilter output buffer of the conversion pair under debugging selected by CPAIR 1 0 It is read only and for debug purpose only 11 10 CPAIR 1 0 Current Pair under Debugging These two bits select the...

Page 303: ... Access Address Register ASRMAA Table 19 14 Debug Control Register 1 ASRDCR1 Bit Field Description 23 0 DSL_TKO 23 0 The Simulated DSL Track Out for the debugging pair These are the 24 LSBs of the simulated DSL track out for the debugging pair The filter processor will use these values to calculate the ASRC output as it detects the rising edge of ASRDCR 8 OUTCLK For debugging these 24 LSBs should ...

Page 304: ... automatically see Table 19 4 and Table 19 8 To access these two registers first assign C00000h to ASRMAA then 1 Read the ASRMAD register which will give the value of TS76KHZ 13 0 then read the ASRMAD register again which will give the value of TS56KHZ 13 0 2 Write the ASRMAD register to assign a value to TS76KHZ 13 0 then write the ASRMAD register again to assign a value to TS56KHZ 13 0 Offset 0x...

Page 305: ...alues for Parameter Registers Register Offset Access Reset Value Recommend Value asrcpm1 0x10 R W 0x00_0000 0x7fffff asrcpm2 0x11 R W 0x00_0000 0x255555 asrcpm3 0x12 R W 0x00_0000 0xff7280 asrcpm4 0x13 R W 0x00_0000 0xff7280 asrcpm5 0x14 R W 0x00_0000 0xff7280 Offset 0x15 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 R TF_FILL 6 0 TF_BA SE 12 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 ...

Page 306: ...e current channel being accessed through the Shared bus for Pair C s output FIFO s usage The value can be any value between 0 ANCC 1 19 16 ACOB The channel counter for Pair B s output FIFO These bits indicate the current channel being accessed through the Shared bus for Pair B s output FIFO s usage The value can be any value between 0 ANCB 1 15 12 ACOA The channel counter for Pair A s output FIFO ...

Page 307: ... six DMA requests are directly connected to the lowest six status bits in the ASRSTR register Table 19 19 Interrupt Vectors Offset Description 0x0 ASRC Pair A input data is needed 0x2 ASRC Pair B input data is needed 0x4 ASRC Pair C input data is needed 0x6 ASRC Pair A output data is ready 0x8 ASRC Pair B output data is ready 0xA ASRC Pair C output data is ready 0xC ASRC Overload 0xE ASRC FP Wait ...

Page 308: ...re filter the low pass bandwidth is at most where Fs is the sampling rate of the input signal to this low pass pre filter Polyphase filter 2 post upsampling filter consisting of a 2 up sampling rate expander zero insertion only with low pass half band FIR filter Output path O0 or direct connection Output path O1 or low pass post decimation filter consisting of a low pass half band FIR filter with ...

Page 309: ... the polyphase filter output is d I1 O0 The signal bandwidth observed before the polyphase filter is at most The signal sampling rate of the polyphase filter output is e I1 O1 The signal bandwidth observed before the polyphase filter is at most The signal sampling rate of the polyphase filter output is f I1 O2 The signal bandwidth observed before the polyphase filter is at most The signal sampling...

Page 310: ...k source duty cycle must be 50 Table 19 22 Pre Processing Post Processing Options Pre_Proc Post_Proc Fsout kHz 32 44 1 48 64 88 2 96 128 192 Fsin kHz 32 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 44 1 0 2 0 1 0 1 0 1 0 1 0 1 0 0 0 0 48 0 2 0 2 0 1 0 1 0 1 0 1 0 1 0 0 64 1 2 0 2 0 2 0 1 0 1 0 1 0 1 0 0 88 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 0 96 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 128 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 ...

Page 311: ... 1 Rx clock ESAI Tx clock Input Clock Divider A Input Clock Divider A AICDA0 AICDA2 Input Clock Divider B Input Clock Divider B AICDB0 AICDB2 AOCDA0 AOCDA2 AOCDB0 AOCDB2 Input Prescaler B Output Prescaler A Output Prescaler B MUX ASRCK1 from PLL ASRCK1 pin ESAI 2 Rx clock ESAI 3 Rx clock ESAI 3 Tx clock ESAI 2 Tx clock Input clock C Input Prescaler C Input Clock Divider C AICDC0 AICDC2 AICPC0 AICP...

Page 312: ...le if a 3 072 MHz clock as ASRCK1 from PLL is connected to ASRC pair A and its desired audio sampling rate is 48 KHz then the divide factor must be 64 48 64 3 072K Next the ASRC Clock Divide register can be configured with the following ASRCDR1 AICDA 0 ASRCDR1 AIDPA 0x6 ASRCDR2 0 For SPDIF If S PDIF is used as a receiver the divide factor should be 128 If S PDIF is used as transmitter the divide f...

Page 313: ...Modes of Operation The chip configuration registers can be accessed by both DSP cores 20 2 Memory Map and Register Definition Table 20 1 shows the memory map for all the chip configuration registers 20 2 1 Memory Map Table 20 1 Chip Configuration Module Memory Map Offset or Address Register Access Reset Value Section Page y FFFFE7 Reserved R 0x00_0000 20 2 2 1 20 3 y FFFFE6 External Memory Burst C...

Page 314: ...FFE7 R W R W EMBC Y FFFFE6 R EPMBC P Space Burst Boundary EYMBC W R Y Space Burst Boundary EXMBC X Space Burst Boundary W LPSC Y FFFFE5 R lplock W R EMC PLL Power Down and clock frequency divide control W PMC Y FFFFE4 R PKG ESAI HCKR Pin Mux Select spdout1_en spdin1_en W R SPDIF Pin Mux Control Timer Pin Mux Control W EPSC Y FFFFE3 R ESAI Pin Switch Control 1 W R ESAI Pin Switch Control 0 W ODBC Y...

Page 315: ...FFFE0 R Shared Bus Arbiter Control W R Shared Bus Arbiter Control W Address Y FFFFE7 Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 1 Reserved Control Register Table 20 3 Field Description Bit Field Description 23 0 Reserved Table 20 2 CFG Register Summary Continued Name 23 22 21 20 19 18 ...

Page 316: ...ternal Memory Burst Buffer Control Register DSP56724 Address Y FFFFE6 Access User Read 23 22 21 20 19 18 17 16 15 14 13 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 3 EMBC Register DSP56725 Table 20 4 Field Description DSP56724 Field Descriptions 23 22 EPMBC Burst control for external P memory space 00 Burst buffer is disabled for the a...

Page 317: ...peripheral space is determined by the boundary bits shown in Table 20 5 7 6 EXMBC Burst control for external X memory space 00 Burst buffer is disabled for the access to external X address space 01 Burst buffer is enabled for the access to external X address space except for X external address space determined by X Space Burst Boundary 10 Burst buffer is enabled for any access to external X addres...

Page 318: ...0 E00000 EFFFFF 1111 F00000 F7FFFF Bit Field Description 23 0 Reserved Write 0 for future compatibility Address Y FFFFE5 Access User Read Write 23 22 21 20 19 18 17 16 15 14 13 12 R lpld W Reset 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 R lpllpde lpllod1 lpllod0 W Reset 0 0 0 0 0 0 0 0 0 0 1 0 Figure 20 4 EMC PLL Status and Control Register PSC DSP56724 Table 20 5 External Peripherals X Y ...

Page 319: ...n DSP56724 Field Descriptions Bit 23 lpld EMC PLL Lock Detection Status bit 1 lock detected 0 lock undetected Bit 22 3 Reserved Write 0 for future compatibility Bit 2 lpllpde EMC PLL Power Down Enable 1 Power Down Enabled 0 Power Down Disabled Bit 1 0 lpllod 1 0 EMC PLL output clock frequency Divide Ratio 00 output clock not divided 01 output clock divided by 2 10 output clock divided by 4 default...

Page 320: ...ermined by the product s package 21 20 Reserved Write 0 for future compatibility 19 ERC3 S PDIF Rx Clock Output via ESAI_3 HCKR Pin Select 0 No S PDIF clock output via HCKR_3 pin 1 Select the S PDIF Rx clock output via the HCKR_3 pin other than external clock when the corresponding ESAI External clock control bit is set Note HCKR_3 pin is not available on DSP56725 80 pin packages 18 Reserved 17 Re...

Page 321: ...8 PSE7 PSE6 PSE5 PSE4 PSE3 PSE2 PSE1 PSE0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 7 ESAI Pin Switch Control Register EPSC Table 20 10 EPSC Field Descriptions Field Description PSE 23 Pin Switch Control bits for ESAI_1 Pin SDO0_1 and ESAI_3 Pin SDO0_3 0 Pin Switch Disabled 1 Pin Switch Enabled PSE 22 Pin Switch Control bits for ESAI_1 Pin SDO1_1 and ESAI_3 Pin SDO1_3 0 Pin Switch Disabled 1 Pin S...

Page 322: ...Enabled PSE 12 Pin Switch Control bits for ESAI_1 Pin SCKR_1 and ESAI_3 Pin SCKR_3 0 Pin Switch Disabled 1 Pin Switch Enabled PSE 11 Pin Switch Control bits for ESAI Pin SDO0 and ESAI_2 Pin SDO0_2 0 Pin Switch Disabled 1 Pin Switch Enabled PSE 10 Pin Switch Control bits for ESAI Pin SDO1 and ESAI_2 Pin SDO1_2 0 Pin Switch Disabled 1 Pin Switch Enabled PSE 9 Pin Switch Control bits for ESAI Pin SDI...

Page 323: ...KR 0 Pin Switch Disabled 1 Pin Switch Enabled PSE 1 Pin Switch Control bits for ESAI Pin FSR and ESAI_2 Pin FSR 0 Pin Switch Disabled 1 Pin Switch Enabled PSE 0 Pin Switch Control bits for ESAI Pin SCKR and ESAI_2 Pin SCKR 0 Pin Switch Disabled 1 Pin Switch Enabled Note See the product pin out information for using these bits to switch the available pins on the DSP56724 or DSP56725 Address Y FFFFE...

Page 324: ...y cleared by hardware when Core 1 DMA 1 write buffer invalidation acknowledge asserted 2 IRB1 Invalidating the read buffer of Core 1 DMA 1 0 Not invalidating the read buffer of Core 1 DMA 1 1 Invalidating the read buffer of Core 1 DMA 1 Writing 1 to this bit will invalidate the read buffer of Core 1 DMA 1 and it is automatically cleared by hardware when Core 1 DMA 1 read buffer invalidation acknow...

Page 325: ...ASRC Soft Reset Trigger Bit Writing 1 to this bit will cause a soft reset of the ASRC Block the reset period is 6 system clock cycles This bit is cleared by hardware after the reset period reaches 6 system clock cycles 1 PSRC1 EMC Soft Reset Trigger Bit Writing 1 to this bit will cause a soft reset of the EMC module the reset period is 6 system clock cycles This bit is cleared by hardware after th...

Page 326: ...method select for peripherals on the shared peripherals bus 15 14 SAC7 Shared Bus Arbiter arbitration method select for shared memory block 7 13 12 SAC6 Shared Bus Arbiter arbitration method select for shared memory block 6 11 10 SAC5 Shared Bus Arbiter arbitration method select for shared memory block 5 9 8 SAC4 Shared Bus Arbiter arbitration method select for shared memory block 4 7 6 SAC3 Share...

Page 327: ...F Data Pin Mux In DSP56725 80 pin packages the SPDIFIN1 input is multiplexed with ESAI_2 s SDO2_SDI3 pin and SPDIFOUT1 is multiplexed with ESAI_2 s SDO3_SDI2 pin Figure 20 12 and Figure 20 13 show the connection ESAI GPIO Port C ESAI_1 GPIO Port E ESAI ESAI_1 internal Clock Connect control ESAI_2 GPIO Port C_2 ESAI_3 GPIO Port E_2 ESAI_2 ESAI_3 internal Clock Connect control esai clock signal esai...

Page 328: ...2 pin is used as the SPDIFOUT1 output and the ESAI_2 input on this pin is disabled When the PMC 15 bit is cleared this pin is controlled by ESAI_2 20 3 3 Soft Reset The chip configuration module contains a soft reset control register used for triggering soft reset to different shared peripherals The bit definitions of the PSRC register describes the functionality of each bit that will trigger a so...

Page 329: ... SCKT1 SCKT0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 14 ESAI Internal Clock Control Register EICCR for Core 0 EICCR_1 for Core 1 Table 20 14 EICCR Field Descriptions Bit Field Description 23 12 Reserved 11 10 HCKR 1 0 ESAI HCKR clock internal connect control Controls the HCKR clock direction between ESAI and ESAI_1 For Core 1 it controls the HCKR clock direction between ESAI_2 and ESAI_3 Core 0 ...

Page 330: ...l Controls the SCKR clock direction between ESAI and ESAI_1 For Core 1 it controls the SCKR clock direction between ESAI_2 and ESAI_3 Core 0 and Core 1 have these bits respectively 1 0 SCKT 1 0 ESAI SCKT clock internal connect control Controls the SCKT clock direction between ESAI and ESAI_1 For Core 1 it controls the SCKT clock direction between ESAI_2 and ESAI_3 Core 0 and Core 1 have these bits...

Page 331: ...ESAI and ESAI_1 EICCR CLOCK_NAME 1 0 Description See 0 0 This is the default value after chip reset there is no internal clock connection between ESAI and ESAI_1 Figure 20 16 0 1 No internal clock connection is between ESAI and ESAI_1 1 0 ESAI_1 clock is connected with ESAI ESAI controls in out the clock pin the clock signal is also input to ESAI_1 block ESAI_1 s corresponding clock pins should be...

Page 332: ...SAI_3 block ESAI_3 s corresponding clock pins should be set as input Figure 20 20 1 1 ESAI_2 clock is connected with ESAI_3 ESAI_3 controls in out the clock pin the clock signal is also input to ESAI_2 block ESAI_2 s corresponding clock pins should be set as input Figure 20 21 Table 20 17 ESAI and ESAI_1 Internal Clock Connections Internal Clock Connection See No Internal Clock Is Connected Betwee...

Page 333: ...11 Figure 20 21 ESAI GPIO Port C ESAI_1 GPIO Port E ESAI clock signal ESAI_1 clock signal ESAI and ESAI_1 Internal Clock Connect Control 10 ESAI clock signal to pin switch control logic with ESAI_2 block ESAI clock signal to pin switch control logic with ESAI_3 block When the clock connect control bits are set to 10 the ESAI_1 clock should be set as input ESAI_1 s clock comes from the ESAI clock p...

Page 334: ...lock signal ESAI_2 and ESAI_3 Internal Clock Connect Control 10 ESAI_3 clock signal to pin switch control logic with ESAI_1 block ESAI_2 clock signal to pin switch control logic with ESAI block When the clock connect control bits are set to 10 ESAI_3 clock should be set as input ESAI_3 s clock comes from the ESAI_3 clock pin but input or output state of this pin is controlled by ESAI_2 ESAI_3 GPIO...

Page 335: ...ch the EMC supports a glueless interface to synchronous DRAM SDRAM SRAM EPROM flash EPROM burstable RAM regular DRAM devices extended data output DRAM devices and other peripherals Support signals for external address latch LALE allows the multiplexing of address with data lines in devices with limited pin counts The EMC includes write protection features and also a bus monitor to ensure that each...

Page 336: ...k interleaving Supports 24 bit SDRAM port size General purpose chip select machine GPCM Compatible with SRAM EPROM FEPROM and other peripherals Supports boot from external memory connected at LCS0 at system reset Supports boot from 8 bit or 24 bit devices External access termination signal GTA Three User Programmable Machines UPMs User specified control signal patterns can be initiated by software...

Page 337: ...ral purpose line 1 O O High LOE LSDRAS LGPL2 GPCM mode output enable SDRAM mode row address strobe UPM mode general purpose line 2 O O O High LSDCAS LGPL3 SDRAM mode column address strobe UPM mode general purpose line 3 O O High LGTA LGPL4 UPWAIT GPCM mode transaction termination UPM mode general purpose line 4 UPM mode external device wait I O I High Z LGPL5 UPM mode general purpose line 5 O High...

Page 338: ...ng N A LCS 7 0 O Chip selects Eight mutually exclusive chip selects are provided State Meaning Asserted Negated Used to enable specific memory devices or peripherals connected to the EMC LCS 7 0 are provided on a per bank basis For example LCS0 is the chip select for memory bank 0 which has the memory type and attributes defined by BR0 and OR0 Timing N A LWE LSDDQM O GPCM write enable SDRAM data m...

Page 339: ... UPM array Timing N A LGTA LGPL4 UPWAIT I O GPCM terminate access General purpose line 4 UPM wait State Meaning Asserted Negated This signal is an input in GPCM mode and is used for transaction termination This signal may also be configured as one of six general purpose output signals when in UPM mode or as an input to force the UPM controller to wait for the memory device Timing N A LGPL5 O Gener...

Page 340: ...ad data driven by an external device Following the last data transfer of a write access LAD 23 0 are again taken into a high impedance state LCKE O External memory clock enable State Meaning Asserted Negated LCKE is the bus clock enable signal CKE for JEDEC standard SDRAM devices This signal is asserted during normal SDRAM operation LCLK O External memory clocks State Meaning Asserted Negated LCLK...

Page 341: ...egister 2 low part R W 0x00_0000 0xFF_FE0B ORH2 Options register 2 high part R W 0x00_0000 0xFF_FE0C BRL3 Base register 3 low part R W 0x00_0000 0xFF_FE0D BRH3 Base register 3 high part R W 0x00_0000 0xFF_FE0E ORL3 Options register 3 low part R W 0x00_0000 0xFF_FE0F ORH3 Options register 3 high part R W 0x00_0000 0xFF_FE10 BRL4 Base register 4 low part R W 0x00_0000 0xFF_FE11 BRH4 Base register 4 ...

Page 342: ...ster high part R W 0x00_0000 0xFF_FE3C MCMRL UPMC mode register low part R W 0x00_0000 0xFF_FE3D MCMRH UPMC mode register high part R W 0x00_0000 0xFF_FE3E 0xFF_FE41 Reserved 0xFF_FE42 Reserved Memory refresh timer prescaler register has no low part 0xFF_FE43 MRTPR Memory refresh timer prescaler register R W 0x00_0000 0xFF_FE44 MDRL UPM data register low part R W 0x00_0000 0xFF_FE45 MDRH UPM data ...

Page 343: ...Read Write Clear 0x00_0000 0xFF_FE5A Reserved Transfer error disable register has no low part 0xFF_FE5B TEDR Transfer error disable register R W 0x00_0000 0xFF_FE5C Reserved Transfer error interrupt register has no low part 0xFF_FE5D TEIR Transfer error interrupt register R W 0x00_0000 0xFF_FE5E TEATRL Transfer error attributes register low part R W 0x00_0000 0xFF_FE5F TEATRH Transfer error attrib...

Page 344: ...4 X FF_FE11 BRH5 X FF_FE15 BRH6 X FF_FE19 BRH7 X FF_FE1D R W R BA W Reset 0x00_0000 Table 21 5 BRHx field Descriptions Bits Name Description 23 10 Reserved 9 0 BA Base address bits 23 14 The upper 11 bits of each base address register are compared to the address on the address bus to determine if the bus master is accessing a memory bank controlled by the memory controller This is used with the ad...

Page 345: ... given type of access X access Y access P access read write or P access instruction fetch This is used with the extended address mask bits ORx XAM 00 Response X access 01 Response Y access 10 Response P access read write 11 Response P access instruction fetch 12 9 Reserved 8 WP Write protect 0 Read and write accesses are allowed 1 Only read accesses are allowed The memory controller does not asser...

Page 346: ...21 8 shows memory bank sizes from 8K words up to 16M words 21 3 2 2 2 Option Registers ORx GPCM Mode Table 21 9 shows the bit fields for ORx when the corresponding BRx MSEL selects the GPCM machine Table 21 8 Memory Bank Sizes in Relation to Address Mask XAM Address Mask Memory Bank Size in Words 11 0000_0000_000 16M 11 1000_0000_000 8M 11 1100_0000_000 4M 11 1110_0000_000 2M 11 1111_0000_000 1M 1...

Page 347: ... EAD W Reset 0x00_0FF7 ORL0 0x00_0000 all other ORLx 1 ORH0 has this value set during reset GPCM is the default control machine for all banks coming out of reset All other option registers have all bits cleared Table 21 12 ORLx GPCM Field Descriptions Bits Name Description 23 16 Reserved 15 AM GPCM address mask bit 13 Masks corresponding BRx bits Masking address bits independently allows external ...

Page 348: ...des the value of CSNT such that CSNT 0 x 01 Reserved 2 10 LCSx is output a half bus clock cycle after the address lines 2 11 LCSx is output a half bus clock cycle after the address lines 4 or 8 10 LCSx is output a quarter bus clock cycle after the address lines 4 or 8 11 LCSx is output a half bus clock cycle after the address lines 8 XACS Extra address to chip select setup Setting this bit increas...

Page 349: ... providing up to 30 wait states Works in conjunction with EHTR to extend hold time on read accesses LCSx only if ACS is not equal to 00 and LWE signals are negated one cycle earlier during writes 1 EHTR Extended hold time on read accesses Indicates with TRLX how many cycles are inserted between a read access from the current bank and the next access TRLX EHTR Meaning 0 0 The memory controller gene...

Page 350: ...s mask bits can be set or cleared in any order in the field allowing a resource to reside in more than one area of the address map 0 Corresponding address bits are masked 1 The corresponding address bits are used in the comparison with address pins Table 21 15 Option Register Low Part x UPM Mode ORLx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ORL0 X FF_FE02 ORL1 X FF_FE06 ORL2 X...

Page 351: ...cted UPM executes burst accesses as a series of single accesses 7 3 Reserved 2 TRLX Timing relaxed Works in conjunction with EHTR to extend hold time on read accesses 1 EHTR Extended hold time on read accesses Indicates with TRLX how many cycles are inserted between a read access from the current bank and the next access TRLX EHTR Meaning 0 0 Normal timing is generated by the memory controller No ...

Page 352: ... Description 23 10 Reserved 9 0 AM SDRAM address mask bits 23 14 Masks correspond to BRx bits Masking address bits independently allows external devices of different size address ranges to be used Address mask bits can be set or cleared in any order in the field allowing a resource to reside in more than one area of the address map AM can be read or written at any time 0 Corresponding address bits...

Page 353: ...xample if BRx XBA 00 or 01 and ORx XAM 10 then the settings permit access from both X and Y 12 10 COLS Number of column address lines Sets the number of column address lines in the SDRAM device 000 7 001 8 010 9 011 10 100 11 101 12 110 13 111 14 9 Reserved 8 6 ROWS Number of row address lines Sets the number of row address lines in the SDRAM device 000 9 001 10 010 11 011 12 100 13 101 14 110 15 ...

Page 354: ...00_0000 Table 21 22 MARH Field Descriptions Bits Name Description 23 10 Reserved 9 0 A The memory address register is used to store A23 A14 of the address which can be output to LAD 23 14 under control of the AMX bits in the UPM RAM word AMX 11 Table 21 23 UPM Memory Address Low Part MARL 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0xFF_FE34 R A W R A W Reset 0x00_0000 Table 21...

Page 355: ...ed 1 Refresh services are required 13 12 OP Command opcode Determines the command executed by the UPMx when a memory access hits a UPM assigned bank 00 Normal operation 01 Write to UPM array On the next memory access that hits a UPM assigned bank write the contents of the MDR into the RAM location pointed to by MAD After the access the MAD field is automatically incremented 10 Read from UPM array ...

Page 356: ...by the same UPMx is also allowed To avoid conflicts between successive accesses to different banks the minimum pattern in the RAM array for a request serviced should not be shorter than the period established by DS 00 1 bus clock cycle disable period 01 2 bus clock cycle disable period 10 3 bus clock cycle disable period 11 4 bus clock cycle disable period 5 3 G0CLx General line 0 control Determin...

Page 357: ... Mode Registers Low Part MxMRL 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAMRL X 0xFF_FE38 MBMRL X 0xFF_FE3A MCMRL X 0xFF_FE3C R RLFx WLFx W R WLFx TLFx MAD W Reset 0x00_0000 Table 21 28 MxMRL Field Descriptions Bits Name Description 23 16 Reserved 15 14 RLFx Read loop field Determines the number of times a loop defined in the UPMx will be executed for a burst or single beat re...

Page 358: ...r a refresh service pattern 0000 16 0001 1 0010 2 0011 3 1110 14 1111 15 5 0 MAD Machine address RAM address pointer for the command executed Each time that the UPM is accessed and the OP field is set to WRITE or READ this field is incremented by 1 Address range is 64 words per UPMx Table 21 29 Memory Refresh Timer Prescaler Register MRTPR 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 359: ... 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0xFF_FE45 R D W R D W Reset 0x00_0000 Table 21 32 MDRH Field Descriptions Bits Name Description 23 16 Reserved 15 0 D Bits 31 16 of the data to be read or written into the RAM array when a write or read command is supplied to the UPM MxMR OP 01 or MxMR OP 10 Table 21 33 UPM Data Register Low Part MDRL 23 22 21 20 19 18 17 16 15 14 13...

Page 360: ...0000 Table 21 36 SDMRH Field Descriptions Bits Name Description 23 15 Reserved 14 RFEN Refresh enable Indicates that the SDRAM requires refresh services 0 Refresh services are not required 1 Refresh services are required 13 11 OP SDRAM operation Selects the operation that occurs when the SDRAM device is accessed 10 8 Reserved Value Meaning Use 000 Normal operation Normal operation 001 Auto refresh...

Page 361: ...SH command after a REFRESH command 000 Reserved 001 3 clocks 010 4 clocks 011 5 clocks 100 6 clocks 101 7 clocks 110 8 clocks 111 16 clocks Table 21 37 SDRAM Machine Mode Register Low Part SDMRL 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0xFF_FE4A R RFCR PRETOACT W R ACTTORW BL WRC BUFCMD CL W Reset 0x00_0000 Table 21 38 SDMRL Field Descriptions Bits Name Description 23 16 Res...

Page 362: ... 011 3 100 4 101 5 110 6 111 7 8 BL Sets the burst length for SDRAM accesses 0 Reserved 1 SDRAM burst length is 8 7 6 Reserved 5 4 WRC Write recovery time Defines the earliest timing for a PRECHARGE command after the last data is written to the SDRAM 00 4 01 Reserved 10 2 11 3 3 Reserved 2 BUFCMD Control line assertion timing If external buffers are placed on the control lines going to both the SD...

Page 363: ...he low part is reserved and the corresponding address should not be used Table 21 39 UPM Refresh Timer URT 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0xFF_FE51 R URT W R URT W Reset 0x00_0000 Table 21 40 URT Field Descriptions Bits Name Description 23 16 Reserved 15 8 URT UPM refresh timer period Determines along with the timer prescaler MRTPR the timer period according to the...

Page 364: ... error bit TESR WP and not affect any other bits in the register the value 0x00_0400 should be written to the register NOTE The TESR register has no low part The low part is reserved and the corresponding address should not be used Table 21 41 SDRAM Refresh Timer SRT 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0xFF_FE53 R SRT W R SRT W Reset 0x00_0000 Table 21 42 SRT Field Desc...

Page 365: ... 3 2 1 0 X 0xFF_FE59 R BM W R WP CS W Reset 0x00_0000 Table 21 44 TESR Field Descriptions Bits Name Description 23 16 Reserved 15 BM Bus monitor time out 0 No external memory monitor time out has occurred 1 External memory monitor time out has occurred No data beat was acknowledged on the bus within BCR BMT x 8 bus clock cycles from the start of a transaction 14 11 Reserved 10 WP Write protect err...

Page 366: ...o Processors Rev 0 21 32 Freescale Semiconductor External Memory Controller EMC Table 21 45 Transfer Error Check Disable Register TEDR 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0xFF_FE5B R BMD W R WPD CSD W Reset 0x00_0000 ...

Page 367: ...art The low part is reserved and the corresponding address should not be used Table 21 46 TEDR Field Descriptions Bits Name Description 23 16 Reserved 15 BMD Bus monitor disable 0 Bus monitor is enabled 1 Bus monitor is disabled 14 11 Reserved 10 WPD Write protect error checking disable 0 Write protect error checking is enabled 1 Write protect error checking is disabled 9 4 Reserved 3 CSD Chip sel...

Page 368: ...ror reporting is enabled 14 11 Reserved 10 WPI Write protect error interrupt enable 0 Write protect error reporting is disabled 1 Write protect error reporting is enabled 9 4 Reserved 3 CSI Chip select error interrupt enable 0 Chip select error reporting is disabled 1 Chip select error reporting is enabled 2 0 Reserved Table 21 49 Transfer Error Attributes Register High Part TEATRH 23 22 21 20 19 ...

Page 369: ...Description 23 4 Reserved 3 2 XA Extended address for the error The address indicates which type of access X Y or P makes the error happen 00 X access 01 Y access 10 P access read write 11 P access instruction fetch 1 Reserved 0 V Error attribute capture is valid Indicates that the captured error information is valid 0 Captured error attributes and address are not valid 1 Captured error attributes...

Page 370: ... P memory space 13 10 Reserved 9 0 A Transaction address A 23 14 for the error Table 21 55 Transfer Error Address Register Low Part TEARL 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0xFF_FE60 R A W R A W Reset 0x00_0000 Table 21 56 TEARL Field Descriptions Bits Name Description 23 16 Reserved 15 2 A Transaction address A 13 0 for the error 1 0 Reserved Table 21 57 Local Bus Con...

Page 371: ...UPM accesses buffer control 01 LBCTL is used as LOE for GPCM accesses only 10 LBCTL is used as LWE for GPCM accesses only 11 Reserved 5 0 Reserved Table 21 59 Local Bus Configuration Register Low Part LBCRL 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0xFF_FE68 R BMT W R BMT W Reset 0x00_0000 Table 21 60 LBCRL Field Descriptions Bits Name Description 23 16 Reserved 15 8 BMT Bus ...

Page 372: ...sing low bus clock frequencies less than 50 When in PLL bypass mode incoming data is captured in the middle of the bus clock cycle 0 The PLL is enabled 1 The PLL is bypassed 14 Reserved 13 12 BUFCMDC Additional delay cycles for SDRAM control signals Defines the number of cycles to be added for each SDRAM command when SDMR BUFCMD 1 00 4 01 1 10 2 11 3 11 10 Reserved 9 8 ECL Extended CAS latency Det...

Page 373: ...his reason GPCM controlled banks are used primarily for boot loading and access to low performance memory mapped peripherals The UPM machine supports refresh timers address multiplexing of the external bus and the generation of programmable control signals for row address and column address strobes to allow for a minimal glue logic interface to DRAMs burstable SRAMs and almost any other type of pe...

Page 374: ...1 4 1 1 Address and Address Space Checking The defined base addresses are written to the BRx registers while the corresponding address masks are written to the ORx registers Each time an external memory access is requested the internal transaction address is compared with each bank Addresses are decoded by comparing the 11 MSBs of the address masked by ORx XAM and ORx AM with the base address for ...

Page 375: ...tion of LALE may be required for SDRAM to transfer a 8 word cache line In the case of UPM the frequency of LALE assertion depends on how the UPM RAM is programmed UPM single accesses typically assert LALE once upon commencement but it is possible to program UPM to assert LALE several times and to change the values of LA 2 0 with and without LALE being involved In general when using the GPCM and SD...

Page 376: ...ch bus cycle is terminated within a reasonable period user defined When a transaction starts the bus monitor starts counting down from the time out value LBCR BMT until a data beat is acknowledged on the bus The bus monitor then reloads the time out value and resumes the count down until the data tenure is completed and then idles if there is no pending transaction Bus monitor error reporting thro...

Page 377: ...ributes for the memory cycle are taken from ORx These attributes include the CSNT ACS XACS SCY TRLX EHTR and SETA fields Table 21 65 shows signal behavior and system response for a write access with CRR CLKDIV 4 or CRR CLKDIV 8 Table 21 66 shows the signal behavior and system response for a read access with CRR CLKDIV 4 or CRR CLKDIV 8 for both personalities Table 21 67 and Table 21 68 show the wr...

Page 378: ...ALE for more than one cycle increases the total cycle count accordingly 0 0 00 0 0 0 0 3 SCY 0 0 10 0 1 4 0 0 3 SCY 0 0 11 0 1 2 0 0 3 SCY 0 1 00 0 0 0 0 3 SCY 0 1 10 0 1 0 0 3 SCY 0 1 11 0 2 0 0 4 SCY 0 0 00 1 0 0 1 4 3 SCY 0 0 10 1 1 4 1 4 1 4 3 SCY 0 0 11 1 1 2 1 4 1 4 3 SCY 0 1 00 1 0 0 1 4 3 SCY 0 1 10 1 1 1 4 1 4 3 SCY 0 1 11 1 2 1 4 1 4 4 SCY 1 0 00 0 0 0 0 3 2 SCY 1 0 10 0 1 1 4 0 0 4 2 SC...

Page 379: ... 1 and CRR EADC 01 Asserting LALE for more than one cycle increases the total cycle count accordingly 0 0 0 00 0 1 4 SCY 0 0 0 10 1 4 1 4 SCY 0 0 0 11 1 2 1 4 SCY 0 0 1 00 0 1 4 SCY 0 0 1 10 1 1 4 SCY 0 0 1 11 2 1 5 SCY 0 1 0 00 0 2 5 SCY 0 1 0 10 1 4 2 5 SCY 0 1 0 11 1 2 2 5 SCY 0 1 1 00 0 2 5 SCY 0 1 1 10 1 2 5 SCY 0 1 1 11 2 2 6 SCY 1 0 0 00 0 5 8 2 SCY 1 0 0 10 1 1 4 5 9 2 SCY 1 0 0 11 1 1 2 5...

Page 380: ...and CRR EADC 01 Asserting LALE for more than one cycle increases the total cycle count accordingly 0 0 00 0 0 0 0 3 SCY 0 0 10 0 1 2 0 0 3 SCY 0 0 11 0 1 2 0 0 3 SCY 0 1 00 0 0 0 0 3 SCY 0 1 10 0 1 0 0 3 SCY 0 1 11 0 2 0 0 4 SCY 0 0 00 1 0 0 0 3 SCY 0 0 10 1 1 2 0 0 3 SCY 0 0 11 1 1 2 0 0 3 SCY 0 1 00 1 0 0 0 3 SCY 0 1 10 1 1 0 0 3 SCY 0 1 11 1 2 0 0 4 SCY 1 0 00 0 0 0 0 3 2 SCY 1 0 10 0 1 1 2 0 0...

Page 381: ... LCSx Negated to Address Change Total Cycles1 1 Total cycles when LALE is asserted for one cycle only ORx EAD 0 ORx EAD 1 and CRR EADC 01 Asserting LALE for more than one cycle increases the total cycle count accordingly 0 0 0 00 0 1 4 SCY 0 0 0 10 1 2 1 4 SCY 0 0 0 11 1 2 1 4 SCY 0 0 1 00 0 1 4 SCY 0 0 1 10 1 1 4 SCY 0 0 1 11 2 1 5 SCY 0 1 0 00 0 2 5 SCY 0 1 0 10 1 2 2 5 SCY 0 1 0 11 1 2 2 5 SCY ...

Page 382: ...figuration The GPCM supports internal generation of transfer acknowledge It allows between zero and 30 wait states to be added to an access by programming ORx SCY and ORx TRLX Internal generation of transfer acknowledge is enabled if ORx SETA 0 If LGTA is asserted externally two bus clock cycles or more before the wait state counter has expired to allow for synchronization latency the current memo...

Page 383: ...or 8 For example when ACS 00 and CSNT 1 LWE is negated one quarter of a clock earlier as shown in Figure 21 6 If CRR CLDIV 2 LWE is negated either coincident with LCSx or one cycle earlier 21 4 2 2 3 Relaxed Timing ORx TRLX is provided for memory systems that require more relaxed timing between signals Setting TRLX 1 has the following effect on timing An additional bus cycle is added between the a...

Page 384: ...CS 1x SCY 0 CSNT 0 TRLX 1 CLKDIV 4 8 Relaxed timing read and write transactions are illustrated in Figure 21 7 and Figure 21 8 The effect of CLKDIV 2 for these examples is only to delay the assertion of LCSx in the ACS 10 case to the LCLK LAD LALE LCSx LBCTL A TA LWE ACS 10 LOE ACS 11 SCY 1 TRLX 1 Address Latched Address Read Data LCLK LAD LALE LCSx LBCTL A TA LWE ACS 10 LOE ACS 11 Address 1 Latch...

Page 385: ...a pair of writes issued consecutively When TRLX and CSNT are set in a write access the LWE strobe signals are negated one clock earlier than in the normal case as shown in Figure 21 9 and Figure 21 10 If ACS 00 LCSx is also negated one clock earlier Figure 21 9 GPCM Relaxed Timing Write XACS 0 ACS 10 SCY 0 CSNT 1 TRLX 1 CLKDIV 4 8 LCLK LAD LALE LCSx LBCTL A TA LWE ACS 10 LOE CSNT 1 Address Latched...

Page 386: ...e delayed along with the assertion of LCSx by programming TRLX 1 LOE negates on the rising clock edge coinciding with LCSx negation 21 4 2 2 5 Extended Hold Time on Read Accesses Slow memory devices that take a long time to disable their data bus drivers on read accesses should choose some combination of ORx TRLX and ORx EHTR Any access following a read access to the slower memory bank is delayed ...

Page 387: ... Fastest Timing Figure 21 12 GPCM Read Followed by Write TRLX 0 EHTR 1 One Cycle Extended Hold Time on Reads LCLK LAD LALE LCSx LBCTL A TA LOE LCSy Bus turnaround Read Data 1 Address 2 Data 2 Latched Address 2 Latched Address 1 Address 1 LCLK LAD LALE LCSx LBCTL A TA LOE LCSy Extended holdBus turnaround Rd Address Latched Read Address Read Data Wr Address Wr Address Wr Data ...

Page 388: ...t GPCM access regardless of the setting of ORx SETA LGTA should be asserted for at least one bus cycle to be effective Note that because LGTA is synchronized bus termination occurs two cycles after LGTA assertion so in case of read cycle the device still must drive data as long as LOE is asserted The user selects whether transfer acknowledge is generated internally or externally LGTA by programmin...

Page 389: ...R0 or OR0 is reconfigured The boot chip select also provides a programmable port size byte boot or word boot which is configured by boot mode pins during reset The boot chip select does not provide write protection LCS0 operates this way until the first write to OR0 and it can be used as any other chip select register after the preferred address range is loaded into BR0 Table 21 69 describes the i...

Page 390: ...efined in SDMR Figure 21 15 shows an example connection between the EMC and a 24 bit SDRAM device with 12 address lines Address signals A 2 0 of the SDRAM connect directly to LA 2 0 address pin A10 connects to the EMC s dedicated LSDA10 signal while the remaining address bits except A10 are latched from LAD 11 3 Figure 21 15 Connection to a 24 Bit SDRAM with 12 Address Lines OR0 AM XAM BCTLD CSNT ...

Page 391: ...ommands SDMR OP Command Description 110 ACTIVATE Latches the row address and initiates a memory read of that row Row data is latched in SDRAM sense amplifiers and must be restored with a PRECHARGE command before another ACTIVATE is issued 011 MODE SET Allows setting of SDRAM options CAS latency and burst length CAS latency depends on the SDRAM device used Although some SDRAMs provide burst lengths...

Page 392: ...ed with a PRECHARGE ALL BANKS command the bus becomes idle and ORx PMSEL 0 in which case all open pages in the current device are closed with a PRECHARGE ALL BANKS command 111 WRITE Latches the column address and transfers data from the data signals to the selected sense amplifier on the SDRAM device as determined by the column address During each successive clock additional data is transferred to...

Page 393: ...s must be connected to the latched address bits and burst address bits LA 2 0 of the EMC with the exception of A10 which has a dedicated connection on LSDA10 LSDA10 is driven with the appropriate row address bit for SDRAM commands that require A10 to be an address 21 4 3 7 SDRAM Device Specific Parameters The software is responsible for setting correct values for device specific parameters that ca...

Page 394: ...e earliest timing for a READ WRITE command after an ACTIVATE command to the same SDRAM bank Figure 21 18 ACTTORW 2 2 Clock Cycles 21 4 3 7 3 Column Address to First Data Out CAS Latency The First Data Out parameter controlled by SDMR CL for latencies of 1 2 or 3 and by CRR ECL for a latency of more than 3 defines the timing for first read data after a column address is sampled by the SDRAM 1111 00...

Page 395: ...eter controlled by SDMR RFRC defines the earliest timing for an ACTIVATE or REFRESH command after a REFRESH command to the same SDRAM device Figure 21 21 RFRC 4 6 Clock Cycles 1111 0000 1111 ZZZZZZZZ RASADD ZZZZZZZZ CAS_ADD D0 D1 D2 LCLK LALE LCSx LSDRAS LSDCAS LSDWE LSDDQM LAD 23 0 D3 XXXX CL 2 READ Command First Data Out 1111 0000 1111 ZZZZZZZZ CASADD D0 RASADD CASADD LCLK LALE LCSx LSDRAS LSDCA...

Page 396: ...als LSDRAS LSDCAS LSDWE and LSDA10 for each SDRAM command Figure 21 22 BUFCMD 1 CRR BUFCMDC 2 21 4 3 8 SDRAM Interface Timing The following figures show SDRAM timing for various types of accesses Figure 21 23 SDRAM Single Beat Read Page Closed CL 3 Figure 21 24 SDRAM Single Beat Read Page Hit CL 3 1111 0000 1111 ZZZZZZ RASADD XXXXXXXX CASADD D3 ZZZZZZZZ LCLK LALE LCSx LSDRAS LSDCAS LSDWE LSDDQM LA...

Page 397: ...M Three Beat Write Page Closed 1111 0000 1111 ZZZZZZZZ ZZZZ ZZZZZZZZ D0 ZZZZZZ LCLK LALE LCSx LSDRAS LSDCAS LSDWE LSDDQM LAD 23 0 COL ADD ROW ADD TA D1 1111 0000 1111 ZZZZZZ ROW ADD ZZZZZZZZ COL ADD ZZZZZZZZ D0 ZZZZZZ LCLK LALE LCSx LSDRAS LSDCAS LSDWE LSDDQM LAD 23 0 TA D1 D2 D3 1111 0000 1111 ZZZZZZZZ COL ADD D0 ZZZZZZZZ LCLK LALE LCSx LSDRAS LSDCAS LSDWE LSDDQM LAD 23 0 TA 1111 0000 1111 ZZZZZZ...

Page 398: ... suppressed by the assertion of LSDDQM For writes that require less than the full burst length the non targeted addresses are protected by driving corresponding LSDDQM bits high inactive on the irrelevant cycles of the burst However system performance is not compromised because if a new transaction is pending the SDRAM controller begins executing it immediately effectively terminating the burst ea...

Page 399: ...ity low and high The low priority request is generated as soon as the refresh timer expires this request is granted only if no other requests to the memory controller are pending If the request is not granted because the memory controller is busy and the refresh timer expires two more times the request becomes high priority and is served when the current memory controller operation finishes 21 4 3...

Page 400: ... period on the chip select lines Figure 21 34 shows the basic operation of each UPM Figure 21 34 User Programmable Machine Functional Block Diagram The following events initiate a UPM cycle Any internal device requests an external memory access to an address space mapped to a chip select serviced by the UPM A UPM refresh timer expires and requests a transaction such as a DRAM refresh 1111 0000 111...

Page 401: ...nternal device s request for a memory access initiates one of the following patterns MxMR OP 00 Read single beat pattern RSS Read burst cycle pattern RBS Write single beat pattern WSS Write burst cycle pattern WBS A UPM refresh timer request pattern initiates a refresh timer pattern RTS An exception caused by a bus monitor time out error occurs while another UPM pattern is running initiates an exc...

Page 402: ...also be inhibited by setting ORx BI Burst performance can be achieved by ensuring that UPM transactions are 8 word aligned with a transaction size being some multiple of 8 word which is a natural fit for a cache line transfer 21 4 4 1 2 UPM Refresh Timer Requests Each UPM contains a refresh timer that can be programmed to generate refresh service requests of a particular pattern in the RAM array F...

Page 403: ...n with any write transaction that hits the corresponding UPM machine The starting address in the RAM array for the pattern is set in the MxMR MAD field Note that transfer acknowledges UTA bit in the RAM word are ignored for software RUN command requests and afterwards the LAD signals remain high impedance unless the normal initial LALE occurs or the RUN pattern causes assertion of LALE to occur on...

Page 404: ...MDR register has already been updated with the desired pattern 9 Perform a dummy write transaction so that a write transaction can now be performed 10 Read check the MxMR MAD bit If the MAD bit is incremented then the previous dummy write transaction has finished Note that if step 1 or step 6 and step 2 or step 7 are reversed then step 3 or step 8 is replaced by the following Read the MxMR registe...

Page 405: ...ed in the current RAM word For CRR CLKDIV 4 or 8 each bit in the RAM word relating to LCSx timing specifies the value of the corresponding external signal at each quarter phase of the bus clock If CRR CLKDIV 2 the external signal can change value only on each half phase of the bus clock If the RAM word in this case LCRR CLKDIV 2 specifies a quarter phase signal change the signal timing generator i...

Page 406: ...figure are UPM outputs The selected LCSx is for the bank that matches the current address Figure 21 39 RAM Array and Signal Generation 21 4 4 4 1 RAM Words The RAM word is a 32 bit micro instruction stored in one of 64 locations in the RAM array It specifies the timing for the external signals controlled by the UPM Figure 21 40 shows the RAM word fields LCLK T1 T2 T3 T4 T1 T2 T3 T4 LGPL0 LGPL2 LGP...

Page 407: ...ld Descriptions Table 21 72 RAM Word Field Descriptions Bits Name Description 31 CST1 Chip select timing 1 Defines the state 0 or 1 of LCSx during bus clock quarter phase 1 if CRR CLKDIV 4 or 8 Defines the state 0 or 1 of LCSx during bus clock half phase 1 if CRR CLKDIV 2 30 CST2 Chip select timing 2 Defines the state 0 or 1 of LCSx during bus clock quarter phase 2 if CRR CLKDIV 4 or 8 Ignored whe...

Page 408: ...tput LGPL4 then G4T1 DLT3 defines the state 0 or 1 of LGPL4 during bus clock quarter phases 1 and 2 first half phase If MxMR GPL4 1 and LGPL4 UPWAIT functions as an input UPWAIT and if a read burst or single read is executed then G4T1 DLT3 defines the sampling of the data bus as follows 0 In the current word the data bus should be sampled at the start of bus clock quarter phase 1 of the next bus c...

Page 409: ...l a handler should negate RAS and CAS to prevent data corruption If EXEN 0 exceptions are ignored by UPM but not by the Local Bus and execution continues After the UPM branches to the exception start address it continues reading until the LAST bit is set in the RAM word 0 The UPM continues executing the remaining RAM words ignoring any internal bus monitor timeout 1 The current RAM word allows a b...

Page 410: ...the same bank until the timer expires The disable timer period is determined in MxMR DSx The disable timer does not affect memory accesses to different banks Note that TODT must be set together with LAST otherwise it is ignored 0 The disable timer is turned off 1 The disable timer for the current bank is activated preventing a new access to the same bank when controlled by the UPMs until the disab...

Page 411: ...emented by one Continued loop execution depends on the loop counter If the counter is not zero the next RAM word executed is the loop start word Otherwise the next RAM word executed is the one after the loop end word Loops can be executed sequentially but cannot be nested Also special care must be taken in the following case LAST and LOOP must not be set together 21 4 4 4 5 Repeat Execution of Cur...

Page 412: ...an address phase on the LAD 23 0 bus with the assertion of LALE for the number of cycles set for LALE in the ORx and CRR registers The LGPL 5 0 signals maintain the value specified in the RAM word during the LALE phase 21 4 4 4 7 Data Valid and Data Sample Control UTA When a read access is handled by the UPM and the UTA bit 1 data is to be sampled by EMC the value of the DLT3 bit in the same RAM w...

Page 413: ...zed by the memory controller as if it were an asynchronous signal The WAEN bit is ignored if LAST 1 in the same RAM word Synchronization of UPWAIT starts at the rising edge of the bus clock and takes at least 1 bus cycle to complete If UPWAIT is asserted and WAEN 1 in the current UPM word the UPM is frozen until UPWAIT is negated The value of external signals driven by the UPM remains as indicated...

Page 414: ...signal which must meet set up and hold times in relation to the rising edge of the bus clock In this case as soon as UPM samples UPWAIT negated on the rising edge of the bus clock it immediately generates an internal transfer acknowledge which allows a data transfer one bus clock cycle later The generation of transfer acknowledge is early because UPWAIT is not re synchronized and the acknowledge o...

Page 415: ...y existing bus turnaround cycle 21 4 4 7 Memory System Interface Example Using UPM Connecting the external memory UPM controller to a DRAM device requires a detailed examination of the timing diagrams representing the possible memory cycles that must be performed when accessing this device This section describes timing diagrams for various UPM configurations using fast page mode DRAM as an example...

Page 416: ... Reserved Bit 6 1 0 0 Reserved Bit 7 1 0 0 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 1 1 1 g1t3 Bit 13 1 1 1 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 22 redo 1 Bit 23 loop Bit 24 0 0 0 exen Bit 25 0 0 0 amx0 Bit 26 1 0 0 amx1 Bit 27 0 0 0 na Bit 28 0 0 0 uta Bit 29 0 0 1 todt Bit 30 0 0 1 last Bit 31 0 0 1 RSS RSS RS...

Page 417: ...rved Bit 6 1 0 0 Reserved Bit 7 1 0 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 0 0 0 g1t3 Bit 13 0 0 0 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 22 redo 1 Bit 23 loop Bit 24 0 0 0 exen Bit 25 0 0 0 amx0 Bit 26 1 0 0 amx1 Bit 27 0 0 0 na Bit 28 0 0 0 uta Bit 29 0 0 1 todt Bit 30 0 0 1 last Bit 31 0 0 1 WSS WSS WSS 1 W...

Page 418: ...t 6 1 1 0 1 Reserved Bit 7 1 0 0 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 1 1 1 1 g1t3 Bit 13 1 1 1 1 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 22 redo 1 Bit 23 loop Bit 24 0 1 1 0 exen Bit 25 0 0 1 0 amx0 Bit 26 1 0 0 0 amx1 Bit 27 0 0 0 0 na Bit 28 0 0 1 0 uta Bit 29 0 0 1 0 todt Bit 30 0 0 0 1 last Bit 31 0 0 0 ...

Page 419: ... Reserved 0 0 0 Bit 5 Reserved 0 0 1 Bit 6 Reserved 0 0 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 22 redo 1 Bit 23 loop 0 0 0 Bit 24 exen 0 0 0 Bit 25 amx0 0 0 0 Bit 26 amx1 0 0 0 Bit 27 na 0 0 0 Bit 28 uta 0 0 0 Bit 29 todt 0 0 1 Bit 30 last 0 0 1 Bit 31 P...

Page 420: ...Reserved 1 Bit 4 Reserved 1 Bit 5 Reserved 1 Bit 6 Reserved 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 22 redo 1 Bit 23 loop 0 Bit 24 exen 0 Bit 25 amx0 0 Bit 26 amx1 0 Bit 27 na 0 Bit 28 uta 0 Bit 29 todt 1 Bit 30 last 1 Bit 31 EXS LCLK LAD LALE LBCTL TA RA...

Page 421: ...pheral Transactions on the EMC start with an address phase where the EMC drives the transaction address on the LAD signals and asserts the LALE signal This can be used to latch the address and then the EMC can continue with the data phase In addition the EMC supports burst transfers not in the GPCM machine LA 2 0 are the burst addresses within a natural 8 word burst To minimize the amount of addre...

Page 422: ...dress and data bus sees the capacitive loading of the data pins of the fast SDRAMs or synchronous SRAMs plus one load for an address latch plus one load for a buffer to the slow memories The loadings of all other memories and peripherals are hidden behind the buffer and the latch The system designer needs to investigate the loading scenario and ensure that I O timings can be met with the loading d...

Page 423: ... Very High Bus Speeds 21 5 1 4 GPCM Timing In the case where a system contains a memory hierarchy with high speed synchronous memories SDRAM synchronous SRAM and lower speed asynchronous memories like flash EPROM peripherals and others then the GPCM controlled memories should be decoupled by buffers to reduce capacitive loading on the bus Those buffers have to be taken into account for the timing ...

Page 424: ...e some time for slow devices the EHTR feature of the GPCM or the programmability of the UPM should be used to guarantee that those devices have stopped driving the bus when the EMC memory controller ends the bus cycle In this case after the previous cycle ends LBCTL goes high and changes the direction of the bus transceiver The EMC then inserts a bus turnaround cycle to avoid contention The extern...

Page 425: ...d for the general purpose chip select machine GPCM to connect to Flash memory If multiple chip selects are configured to support SDRAM on the EMC each SDRAM device should have the same timing parameters This means that all option registers ORn for the SDRAM chip selects should be programmed exactly the same NOTE Although in principal it is possible to mix timing parameters combinations are limited...

Page 426: ... 5 3 3 Example of SDRAM Usage This section shows examples of the use of EMC SDRAM machine 21 5 3 3 1 Maximum Row Number Due to Bank Select MUX SDMR BSMA is used to multiplex the bank select address The BSMA field and corresponding multiplexed address are shown below 000 LA17 LA16 001 LA16 LA15 111 LA10 LA9 Note that LA17 is the latched value of LAD17 The highest address pins that the bank selects ...

Page 427: ...thout requiring a new board layout 21 5 3 3 3 SDRAM of 256 Mbit Figure 21 54 shows a SDRAM of 256 Mbit Note that all of the circuit diagrams mainly show the connections and do not guarantee signal integrity Figure 21 54 256 Mbit SDRAM Diagram Consider the following SDRAM organization The 24 bit port size is combined with two 16 bit devices All 16 bits of the first device and 8 bits of the LSBs of ...

Page 428: ...refreshed and therefore data is not maintained This power down mode is invoked by driving CKE low while all internal banks are idle note that the banks must be precharged first Figure 21 55 shows the timing Figure 21 55 SDRAM Power Down Mode Timing Table 21 75 Logical Address Bus Partitioning A 23 11 A 10 9 A 8 0 Row Bank select Column Table 21 76 SDRAM Device Address Port During Row Address Phase...

Page 429: ...low the device refreshes itself and does not need to see any refreshes from the EMC To exit self refresh CKE simply has to be pulled high Note that after returning from self refresh mode the SDRAM needs a supplier specific time before it can accept new commands and the auto refresh mechanism has to be started again Figure 21 56 shows this timing The SDRAM controller always uses 200 EMC clocks whic...

Page 430: ...he edges of the LCLK signal such that the bus clock arrives at external RAM devices synchronously with respect to the EMC after pad delay and PCB flight time have been accounted for In practice this requires rising edges of LCLK to emerge from 72x early with respect to received data sample points so that set up margins for EMC reads are increased The read path performance is typically the most cri...

Page 431: ...r 21 97 Figure 21 57 EMC De Skew PLL Fout SDRAM Latch Clock Generator De skew PLL LCKE LSYNC_OUT LSYNC_IN LALE CLK ADDR LCLK CMD Command OE CKE DQ LAD EMC Chip Configuration Registers DFF DFF DFF DFF Fin Fref EMC PLL Control Status Reg Keep PCB wire length of equal to that of LSYNC_OUT LSYNC_IN LCLK CLK DQ LAD DFF ...

Page 432: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 21 98 Freescale Semiconductor External Memory Controller EMC ...

Page 433: ...le break points are defined on different DSPs in a multi DSP design you are able to determine which DSP core initiated the entering of the debug state To support this feature two JTAG modules are daisy chained and it looks like two single core devices to the outside world The instruction length of each JTAG is 4 bits for a correct Update IR operation an 8 bit shift from TDI is required JTAG 0 only...

Page 434: ...or a given circuit board test by effectively reducing the boundary scan register to two bypass cells Disables the output drive to pins during circuit board testing Boundary Scan Cells Chip ID Register Bypass Register Core 1 OnCE Module Instruction Decoder 4 Bit Instruction Register Bypass Register Core 0 OnCE Module Instruction Decoder 4 Bit Instruction Register TDI JTAG 1 JTAG 1 JTAG 0 TAP Contro...

Page 435: ...on 4 b0010 IDCODE 4 b1010 Customized test instruction 4 b0011 CLAMP 4 b1011 Reserved 4 b0100 Hi Z 4 b1100 Customized test instruction 4 b0101 Reserved 4 b1101 Customized test instruction 4 b0110 ENABLE_ONCE 4 b1110 Customized test instruction 4 b0111 DEBUG_REQUEST 4 b1111 BYPASS Table 22 2 JTAG 0 Supported Instructions jtag_ins 3 0 Description jtag_ins 3 0 Description 4 b0000 Reserved 4 b1000 Rese...

Page 436: ...criptions Name Function I O Reset Pull Up TCK The external clock that synchronizes the test logic I Pull Up TDI Receives serial test instruction and data which is sampled on the rising edge of TCK and has an internal pull up resistor Register values are shifted in Least Significant Bit LSB first I Pull Up TRST Initializes the test controller asynchronously TRST has an internal pull up resistor I F...

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