Freescale Semiconductor PXR4030, Reference Manual

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Introduction
1-12 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
• eTPU result interface
— Allows any ADC result to be exported to eTPU for use with reaction channels
• Support for an additional 64 – 8 = 56 channels via external multiplexing
1.2.13 Serial peripheral interface module (SPI)
The PXR40 includes four serial peripheral interface (SPI) blocks that provide a synchronous serial
interface for communication to external devices. The SPI features the following:
• Supports pin count reduction through serialization and deserialization of eTPU and eMIOS
channels and memory-mapped registers
• Channels and register content are transmitted using a SPI protocol
— The protocol is completely configurable for baud rate, polarity, phase, frame length, chip select
assertion, etc.
— Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or
GPIO signals
• Can be configured to serialize data to an external device that is compatible with the Microsecond
Bus protocol
• SPI pins support 5 V logic levels or low voltage differential signalling (LVDS) to improve
high-speed operation on data and clock signals
The SPIs have multiple configurations:
• Serial peripheral interface (SPI) configuration where the SPI operates as an up-to-16-bit SPI with
support for queues
• Deserial serial interface (DSI) configuration where the SPI serializes as many as 32 bits from
eTPU, eMIOS, or GPIO output channels and deserializes the received data by placing it on the
eTPU, eMIOS, or GPIO input channels
• Combined serial interface (CSI) configuration where the SPI operates in both SPI and DSI
configurations interleaving DSI frames with SPI frames, giving priority to SPI frames
• Enhanced deserial serial interface (DSI) configuration where SPI serializes as many as 32 bits with
three possible sources per bit
— eTPU, eMIOS, new virtual GPIO registers as possible bit source
— Programmable inter-frame gap in continuous mode
— Bit source selection allows microsecond bus downlink with command or data frames as large
as 32 bits
— Microsecond bus dual receiver mode
For queued operations, the SPI queues reside in system memory external to the SPI. Data transfers between
the memory and the SPI FIFOs are accomplished through the use of the eDMA2 controller or through host
software.