RapidIO Interface Basics
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
16-21
For the following discussion, RapidIO address[0–30] consists of xambs[0–1] and the
address[0–28] fields as defined in the RapidIO request packet format. The RapidIO address is a
31-bit double-word physical address (or a 34-bit byte address). The ATMU translated
address[0–32] is a 33-bit double-word physical address (or 36-bit byte address).
The ATMU window hit definition and RapidIO address translation are as follows:
4 KB window size (smallest window size):
— A window hit is defined as {BEXADD[0–1], BADD[0–19]} matching RapidIO
address [0–21].
—
Internal interconnection addr[0–32] =
{TREXAD[0–3], TRAD[0–19], RapidIO
address[22–30]}.
8 KB window size:
— A window hit is defined as {BEXADD[0–1], BADD[0–18]} matching RapidIO
address [0–20].
—
Internal interconnection addr[0–32] =
{TREXAD[0–3], TRAD[0–18], RapidIO
address[21–30]}.
16 KB window size:
— A window hit is defined as {BEXADD[0–1], BADD[0–17]} matching RapidIO
address [0–19].
—
Internal interconnection addr[0–32] =
{TREXAD[0–3], TRAD[0–17], RapidIO
address[20–30]}.
Window sizes 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16
MB, 32 MB, 64 MB, 128 MB, 256 MB, 512 MB, 1GB, 2 GB are not shown.
4 GB window size:
— A window hit is defined as {BEXADD[0–1]} matching RapidIO address [0–1].
—
Internal interconnection addr[0–32] =
{TREXAD[0–3], RapidIO address[2–30]}.
8 GB window size:
— A window hit is defined as {BEXADD[0]} matching RapidIO address0.
—
Internal interconnection addr[0–32] =
{TREXAD[0–2], RapidIO address[1–30]}.
16 GB window size (largest size):
— A window hit is defined as any RapidIO address.
—
Internal interconnection addr[0–32] =
{TREXAD[0–1], RapidIO address[0–30]}.
16.2.5.4.1 Hits to Multiple ATMU Windows
If a request hits multiple ATMU windows, window 1 has the highest priority of the five inbound
ATMU windows (windows 1–4, default). Window 2 has the next highest priority, followed by
windows 3 and 4. The default window has the lowest priority.
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...