RapidIO Interface Basics
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
16-11
— addr[0–32] = {CCSRBAR[0–15], 0b00000000000000000} + {0b0000,
0b000000000000, RapidIO address[14–30]}.
If the NREAD/NWRITE_R access hits an inbound ATMU window as well, the LCSBA1CSR
window has priority in determining the RapidIO address translation. If an NWRITE/SWRITE
request hits the LCSBA1CSR window, an illegal transaction decode error is generated and
logged.
16.2.4.3 RapidIO Maintenance Accesses
MAINT requests can be used to access RapidIO configuration register space via the 21-bit
configuration offset field (config_offset) from the RapidIO maintenance packet. The RapidIO
address translation is performed via two additions:
Adding a 128 KB multiple that represents the local physical address offset for the RapidIO
configuration register space (RCAO).
Adding the RapidIO packet configuration offset value that represents an index into the
RapidIO configuration register space from the start of the device local configuration
register space.
The 128 KB local physical address offset is a RapidIO port-common value and is provided by the
system configuration input RapidIO_config_addr_offset[0–4]. The RapidIO address translation
is as follows:
addr[0–32] = { {CCSRBAR[0–15], 0b00000000000000000} + {0b0000, 0b0000000000,
rapidio_config_addr_offset[0–4], 10b0000} + {0b0000, 0b0000000000000000,
config_offset[8–20]} }
addr[0–32] = { {CCSRBAR[0–15], 0b00000000000000000} + {0b0000, 0b0000000000,
rapidio_config_addr_offset[0–4]}, 0b0, config_offset[8–20] }
The index into RapidIO configuration register space is represented by config_offset[8–20] only;
bits for config_offset[0–7] are ignored.
16.2.4.3.1 Guidelines
The RapidIO endpoint limits configuration register space requests to 32-bit data accesses. If the
order of completion is important, assume that inbound configuration accesses are incomplete
until an appropriate response is received. It is suggested that only one outstanding configuration
request be active at a time to ensure that requests are completed in the intended order. For
inbound configuration write results that are immediately used by another transaction, perform an
inbound configuration read immediately after the configuration write to ensure that the
transaction uses the updated value of the accessed configuration register.
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...
