Freescale Semiconductor MSC8144E, Reference Manual

Page: 490 / 1374

MSC8144E Reference Manual, Rev. 3
12-38 Freescale Semiconductor
DDR SDRAM Memory Controller
12.7.5 DDR SDRAM Timing Configuration Register 1 (TIMING_CFG_1)
TIMING_CFG_1 sets the number of clock cycles between various SDRAM control commands.
TIMING_CFG_1 DDR SDRAM Timing Configuration Register 1 Offset 0x0108
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— PRETOACT ACTTOPRE — ACTTORW CASLAT
Type R R/W R/W R R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFREC — WRREC — ACTTOACT — WRTORD
Type R/W R R/W R R/W R R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-20. TIMING_CFG_1 Field Descriptions
Bits Reset Description Settings
—
31
0 Reserved. Write to zero for future compatibility.
PRETOACT
30–28
0 Precharge-to-Activate Interval (t
RP
)
Specifies the minimum number of clock cycles between a
precharge command and an activate or refresh command. This
number is calculated from the AC specifications of the SDRAM.
This field must be programmed for proper operation of the DDR
Controller.
000 Reserved.
001 1 clock
010 2 clock cycles.
011 3 clock cycles.
100 4 clock cycles.
101 5 clock cycles.
110 6 clock cycles.
111 7 clock cycles.
ACTTOPRE
27–24
0 Activate to Precharge Interval ( t
RAS
)
Specifies the minimum number of clock cycles between an
activate command and a precharge command. This number is
calculated from the AC specifications of the SDRAM.
This field must be programmed for proper operation of the DDR
Controller.
0000 16 clock cycles.
0001 17 clock cycles.
0010 18 clock cycles.
0011 19 clock cycles.
0100 4 clock cycles.
0101 5 clock cycles.
0110 6 clock cycles.
0111 7 clock cycles.
…
1111 15 clock cycles.
—
23
0 Reserved. Write to zero for future compatibility.
ACTTORW
22–20
0 Activate to Read/Write Interval for SDRAM (t
RCD
)
Specifies the minimum number of clock cycles between an
activate command and a read or write command. This interval is
calculated from the AC specifications of the SDRAM.
This field must be programmed for proper operation of the DDR
Controller.
000 Reserved.
001 1 clock cycle.
010 2 clock cycles.
011 3 clock cycles.
100 4 clock cycles.
101 5 clock cycles.
110 6 clock cycles.
111 7 clock cycles.