Freescale Semiconductor MSC8144E, Reference Manual

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M3 Memory
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 11-23
bits of memory. The ECC is calculated for every write access. Reads from the memory use the
ECC to correct the data. The ECC mechanism of the M2 can detect and correct a single error, and
in that case, generate an interrupt toward the DSP cores.
The reservation atomic operation (bmtset instruction) is performed in two stages: a read of a
certain address content and a write of the modified content back to the original address. Between
these two accesses the atomic operation is defined as open. A write access by another DSP core
subsystem or external hosts to the same address causes the atomic operation to fail, and the DSP
core subsystem atomic write operation to M2 memory is not performed. The systems arbiter
allows one such open atomic operation at a time. Other cores requesting an atomic operation are
serviced only after the current atomic operation is closed.
Note: Atomic operations are only supported in M2 memory and not in any other memory.
11.6 M3 Memory
The 10 MB M3 memory can be used for both program and data and eliminates the need for an
external memory in a variety of applications, thus reducing board space, power dissipation, and
cost. The M3 memory has a 128-bit wide port and runs at 400 MHz using dense memory
technology. The M3 memory supports partial, full, and burst accesses. The M3 memory includes
hidden refresh with a low probability of conflict with core accesses, and it supports burstable
accesses. The M3 memory is fully ECC protected.
The M3 memory uses a novel embedded DRAM (eDRAM) of 20 macrocells of 4 Mb each to
total 80 Mb of user memory with a bidirectional data bus of 128-bit. The memory is located
between addresses 0xD0000000 and 0xD09FFFFF in the MSC8144E memory map. The
eDRAM memories operate at 100 MHz frequency and there is an internal SRAM controller that
enables access with bursts of 4
×
128-bit to generate a sustained bandwidth of 128-bit at 400
MHz between the M3 memory and the rest of the MSC8144E device.
As a DRAM, the memory must be refreshed. The whole refresh operation occurs in parallel to
regular accesses and is almost completely hidden from the user. The time is partitioned to time
slots of 40 cycles. For each time slot, only one row is refreshed on every 2 MB section. The
refresh is delayed until there is a user access in this same time slot and then the refresh is
performed in parallel to the user access and on a different port. If the line to be refreshed in this
time slot is in a different 128 KB sub-module than the user access, the actions are performed in
parallel. If they are to the same 128 KB sub-module, the refresh is delayed until there is another
user access in the same time slot. If there is no user access during the time slot, the controller
forces a refresh condition. If a user access is requested during the refresh period, it is delayed by
up to 4 cycles. The result is that the access to the M3 memory is not deterministic and a refresh
conflict can increase the latency by up to 4 cycles.