L2 Instruction Cache
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
11-15
11.4.6.5.2 PLRU Bit Updates
Each time a cache line is accessed, it is tagged as the most recently used way of the index. For
every line hit in the cache or when a new line is allocated, the PLRU bits for the index are
updated using the rules specified in Table 11-2.
Note:
Only three PLRU bits are updated for any access.
11.4.6.5.3 PLRU Bits In Partial Lock
Partial lock is supported by freezing some of the PLRU bits according to the lock configuration.
The frozen bits prevent some of the L2 ICache lines to be replaced and re-allocated for new miss
access. At least two cache ways (2 lines in each index) are open in any partial lock configuration.
In case of global lock all ways are locked.
11.4.6.5.4 PLRU Inverse Mechanism
PLRU bit status determines which line is next to allocate. The user can change this status (and by
that change the order in which the lines are allocated) by using the inverse mechanism. The
inverse operation is initiated by setting the L2IC_CR1[INV] bit. When you initiate inverse
operation, all the PLRU status bit change their state, causing the allocation sequence to be
inverted.
11.4.6.6 L2 ICache Sweep Operation
The L2 ICache sweep operation supports software coherency by enabling data invalidation for a
specific address space programmed in the cache registers. Invalidation is useful if an instruction
in the cache array will not be used, and required if the data in the system level memory was
updated subsequent to the last cache fetch. The L2 ICache sweep operation uses a dedicated
hardware counter and address comparators. The counter checks each and every cache valid line
cycle by cycle (one line per cycle), and compares the line address, which is a combination of its
Tag and Index, to an address range defined in dedicated registers. The sweep operation
Table 11-2. PLRU Bit Update Rules
Line access
New State of the PLRU Bits
B0
B1
B2
B3
B4
B5
B6
L0
1
1
No change
1
No change
No change
No change
L1
1
1
No change
0
No change
No change
No change
L2
1
0
No change
No change
1
No change
No change
L3
1
0
No change
No change
0
No change
No change
L4
0
No change
1
No change
No change
1
No change
L5
0
No change
1
No change
No change
0
No change
L6
0
No change
0
No change
No change
No change
1
L7
0
No change
0
No change
No change
No change
0
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...
