Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
11-4 Freescale Semiconductor
Internal Memory Subsystem
11.2 Instruction Channel (ICache and IFU)
The Instruction Channel comprises the Instruction Cache (ICache) and the Instruction Fetch Unit
(IFU). This channel provides the core with instructions that are stored in higher-level memory.
The ICache, which operates at core speed, stores recently accessed instructions. Whenever an
addressed instruction (from the cacheable memory area) is found in the array, it is immediately
made available to the core (ICache hit). When the required address is not found in the array, it is
loaded to the ICache from the external (not part of the DSP core subsystem) memory by the IFU
(ICache miss). The IFU operates in parallel to the core to implement a pre-fetch algorithm that
loads the ICache with information that with high probability will be needed soon. This action
reduces the number of cache misses. Whenever an instruction is addressed from a non-cacheable
area, the IFU fetches it directly to the P bus of the core without writing it to the cache.
Instruction channel features include:
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Aligned 128-bit P core accesses.
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Concurrent cacheable and non-cacheable accesses, as identified in the MMU based on the
address ranges.
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Task-extended virtually addressed cache. The 8-bit task ID from the MMU is stored as
part of the line tag that allows a task-specific cache image that is not overridden by other
tasks that use the same virtual address. This feature can support multi-task mechanism.
This extended tag is named the ETAG.
„
Cacheable shared memory between tasks marked by the MMU according to the memory
range, and stored in the cache with TASKID 0.
„
Cache hit access without wait states (except during memory conflicts).
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Issues 128-bit accesses to the higher level memory when a cache miss occurs.
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Programmable to issue pre-fetch accesses upon cache miss that fetches data to the end of
the cache line (256 bytes).
— Pre-fetching is aborted in case of a new miss on a burst size boundary.
— Programmable burst size of 1 or 4 VBRs.
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A miss access identified as a prefetch by the prefetch hit stalls the core to reduce the
number of wait states relative to a simple miss.
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Pseudo-LRU (PLRU) as the cache line replacement mechanism (LRM).
„
Partial lock allows locking of a subset of cache lines based on ways boundaries to reduce
the cache restoration penalty of a restored task. Instructions can be locked in the cache,
preventing the thrashing of instructions that have expected reuse. This mechanism is
useful during rapid task switching and prevents a situation in which a task thrashes
important instructions associated with other tasks.
„
Global lock allows locking of all cache lines to reduce the cache restoration penalty of a
restored task. In this case, the cache does not serve cache misses.