Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
26-132 Freescale Semiconductor
Security Engine (SEC)
26.5.8.7 AESU Interrupt Mask Register (AESUIMR)
The AESU Interrupt Mask Register controls the result of detected errors. For a given error (as
defined in Section 26.4.3.6, AESU Interrupt Status Register, on page 26-43), if the corresponding
bit in this register is set, then the error is ignored; no error interrupt occurs and the Interrupt
Status Register is not updated to reflect the error. If the corresponding bit is not set, then upon
—
3
0 Reserved. Write to zero for future compatibility.
IFO
2
0 Input FIFO Overflow
If set, the AESU input FIFO was pushed while
full.
Note:
When operated through
channel-controlled access, the SEC
implements flow control, and FIFO
size is not a limit to data input. When
operated through core processor-
controlled access, the AESU cannot
accept FIFO inputs larger than 256
bytes without overflowing.
0 No input FIFO overflow error detected.
1 Input FIFO overflow error.
OFU
1
0 Output FIFO Underflow
If set, the AESU output FIFO was read while
empty. 0 No output FIFO underflow error detected.
1 Output FIFO underflow error.
—
0
0
Reserved. Write to zero for future compatibility.
AESUIMR AESU Interrupt Mask Register Offset 0xC4038
Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
Field —
Type R
Reset 0x0000
Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Field —
Type R
Reset 0x0000
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field —
Type R
Reset 0x0000
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field — ICE — IE ERE CE KSE DSE ME AE OFE IFE — IFO OFU —
Type R
Reset 0x1000
Table 26-46. AESUISR Field Descriptions (Continued)
Name Reset Description Settings