Freescale Semiconductor MSC8144E, Reference Manual

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Memory Controller
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 3-11
3.4 Memory Controller
Refer to the memory controller chapter for details on configuring these signals. To support DDR
DRAM external memory, the memory controller uses SSTL2+ signal levels.
Table 3-6. Memory Controller Signals
Signal Name Type Description
MA[15–0] Output Address Bus
The memory interface address bus used to connect to external memory devices. MA0 is
the lsb of the address driven by the DDR controller.
MBA[2–0] Output Bank Address
Selects the DDR DRAM bank. Each DDR SDRAM can support four or eight logically
addressable sub-banks. MBA0 must connect to bit zero of the SDRAM input bank
address. This line is asserted during the mode register set command to specify the
extended mode register.
MDQ[31–0] Input/
Output
Data Bus
The MSC8144E device drives the bus during write cycles and the external memory
drives the bus during read cycles.
MDM[3–0] Output DDR SDRAM Data Output Mask
Masks unwanted data bytes transferred during a burst write. These signals are used to
support sub-burst-size transactions (such as single-byte writes) on SDRAM in which all
transactions occur in multi-byte bursts. MDM0 corresponds to the MSB and MDM3
corresponds to the LSB.
MDQS[3–0] Input/Output DDR SDRAM DQS
Strobe for byte-lane data capture. The signals are inputs driven by the DDR SRAM with
read data and outputs driven by the DDR controller with write data. The data strobes
may be single-ended or differential.
MDQS[3–0] Input/Output DDR SDRAM DQS Complement
Complement strobe for byte-lane data capture. The signals are inputs driven by the DDR
SRAM with read data and outputs driven by the DDR controller with write data. The data
strobes may be single-ended or differential.
MCK[2–0] Output DDR Clock Out
The DDR clock output. Each signal is part of a differential pair.
MCK[2–0
]
Output DDR Clock Out Inverted
The inverted DDR clock. Each signal is part of a differential pair.
MCKE[1–0] Output Clock Enable
When asserted, this signal enables the DDR clock for the DDR DRAM.
MRAS Output Row Address Strobe
Connects to DDR DRAM RAS input. This line is asserted for activate commands and is
used for mode register set and refresh commands.
MCAS Output Column Address Strobe
Connects to DDR DRAM CAS input. This line is asserted for read or write transactions
and for mode register set, refresh, and precharge commands.
MWE Output Write Enable
Connects to DDR DRAM WE input.
MCS[0–1] Output Chip Select 0–1
Enables specific memory devices or peripherals connected to the bus.
MECC[7–0] Input/Output Error Checking and Correction Codes
As outputs, represent the state of ECC driven by the DDR controller on writes. As inputs,
represents the ECC driven by the DDR SDRAMs on reads.