Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
20-26 Freescale Semiconductor
UART
20.6.2 SCI Control Register (SCICR)
SCICR SCI Control Register Offset 0x08
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOOPS — RSRC M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 20-9. SCICR Bit Descriptions
Name Reset Description Settings
—
31–16
0 Reserved. Write to zero for future compatibility.
LOOPS
16
0 Loop Select Bit
Disables the path from URXD to the receiver input for loop
(RSRC = 0) or single-wire mode (RSRC =1). See Table
20-10. The transmitter and the receiver must be enabled to
use the loop functions. The receiver input is determined by
the RSRC bit. The transmitter output is controlled by
SCIDDR[DDRTX] bit. If the data direction bit
(SCIDDR[DDRTX]) for UTXD is set and LOOPS = 1, the
transmitter output drives UTXD. If the data direction bit is
clear and LOOPS =1, the SCI transmitter does not drive
UTXD. 1 Loop operation enabled.
0 Normal operation enabled.
—
14
0 Reserved. Write to zero for future compatibility.
RSRC
13
0 Receiver Source Bit
When LOOPS = 1, determines the internal feedback path for
the receiver. 1 Receiver input connects to
UTXD.
0 Receiver input internally
connected to transmitter
output.
M
12
0 Data Format Mode Bit
Determines whether data characters are eight or nine bits
long. 1 One start bit, nine data bits,
one stop bit.
0 One start bit, eight data bits,
one stop bit.
WAKE
11
0 Wake
Determines which condition wakes up the SCI: a logic 1
(address mark) in the most significant bit position of a
received data character or an idle condition on URXD (10
consecutive logic 1s if M = 0 or 11 consecutive logic 1s if
M=1). 1 Address mark wake-up.
0 Idle line wake-up.