Freescale Semiconductor MPC5604B, Quick Start Manual

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INPLATCH, INPCMP and INPSAMP. The OFFSHIFT field is only available for precision channels
(CTR[0]) and it allows selecting how the last bit of the converted data field should behave:
- 00: The transition between 0x000 and 0x001 happens when the input is equal to 1LSB.
- 01: The transition between 0x000 and 0x001 happens when the input is equal to ½ LSB.
- 10: The transition between 0x000 and 0x001 happens when the input is equal to 0.
There are two register for controlling the presampling phase, the first one is the Presampling
Control Register (PSCR), it has the following fields: PREVAL0, PREVAL1, PREVAL2 (respectively
for different input groups) for selecting between two reference voltages 𝑉
SS_HV_ADC
(00) and
𝑉
DD_HV_ADC
(01). The PRECONV bit which enables the conversion of the presampled value (for
verification issues).
The other registers related to the presampling are the Presampling Registers (PSR[0…2]) which
can enable the presampling phase for a particular channel. Each PSR register corresponds to a
type of inputs, and PSR[0] and PSR[1] contain fields PRES0 to PRES15 (for precision and
standard channels) and PSR[2] contains fields PRES0 to PRES31 (for external channels). Writing
‘1’ to a PRESn bit enables the channel that corresponds to it.
2.4. Interrupt Registers
The Interrupt Status Register (ISR) contains the flag bits of the interrupts generated by the ADC
peripheral. There are five flag bits that are set when an interrupt is raised and they have to be
cleared by writing ‘1’, these are:

EOCTU: End of CTU conversion,

EOC: end of channel conversion,

ECH: end of chain conversion,

JEOC: End of injected channel
conversion,
 JECH: End of injected chain conversion.
There are also individual interrupt flags for each channel, for instance we have Channel Pending
Registers (CEOCFR[0…2], for different input types) with the first two having each 16 fields from
EOC_CH0 to EOC_CH15, and the last register having 32 fields for external channels from
EOC_CH0 to EOC_CH31. These flags are set when the measure of the channel is completed, and it
can be cleared by writing ‘1’.
These interrupt flags are maskable using mask registers, the ISR flags can be masked using the
Interrupt Mask Register, with 5 bits for enabling the ISR flags (MSKEOCTU, MSKEOC …
MSKJECH). The CEOCFR[0…2] registers’ flags can be masked using Channel Interrupt Mask
Registers (CIMR[0…2]), containing CIM0…CIM15( or CIM31) fields.
2.5. Watchdog Registers
There are a few registers for configuring the analog watchdog, the Threshold Control Registers
(TRC[0…3]) for each watchdog, with a threshold enable bit (THREN) for enabling the detection
on a channel selected using THRCH (a 7-bit field).
Then there are the Threshold Registers (THRHLR[0:3]), each containing a higher threshold
value field (THRH) and a lower one (THRL), as 10-bit fields. By default, THRL=0x000 and
THRH=0x3FF.