Freescale Semiconductor MPC5565, Reference Manual

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Signal Description
MPC5565 Microcontroller Reference Manual, Rev. 1.0
2-32 Freescale Semiconductor
2.3.8.18 External Trigger / GPIO
ETRIG[0:1]_GPIO[111:112]
External trigger signals trigger a software or hardware event. The eQADC can detect rising edge, falling
edge, high level, and low level on each of the external trigger signals. The eQADC also supports
configurable digital filters for these external trigger signals.
The eQADC external trigger input pins can be connected to the eTPU, the eMIOS, or an external signal.
The source is selected by configuring the eQADC trigger source in the SIU_ETISR register. Refer to
Table 6-132 .
ETRIG[0] is the external trigger for CFIFO0, CFIFO2, and CFIFO4, and ETRIG[1] serves as the external
trigger for CFIFO1, CFIFO3, and CFIFO5.
GPIO[111:112] are general purpose input/output functions.
These signals are not supported in the 324 package.
2.3.8.19 Voltage Reference High
V
RH
V
RH
is the voltage reference high input pin for the eQADC.
2.3.8.20 Voltage Reference Low
V
RL
V
RL
is the voltage reference low input pin for the eQADC.
2.3.8.21 Reference Bypass Capacitor
REFBYPC
REFBYPC is a bypass capacitor input for the eQADC. The REFBYPC pin is used to connect an external
bias capacitor between the REFBYPC pin and V
RL
. The value of this capacitor must be 100nF. This bypass
capacitor is used to provide a stable reference voltage for the ADC.
2.3.9 Enhanced Time Processing Unit (eTPU) Signals
2.3.9.1 eTPU A TCR Clock / External Interrupt Request / GPIO
TCRCLKA_IRQ[7]_GPIO[113]
TCRCLKA_IRQ[7]_GPIO[113] is the TCR clock input for the eTPU A module. The alternate function is
an external interrupt request input for the SIU module.