Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-10 Freescale Semiconductor
18.3 Memory Map and Register Definition
This section provides memory maps and detailed descriptions of all registers. Data written to or read from
reserved areas of the memory map is undefined.
18.3.1 eQADC Memory Map
This section provides memory maps for the eQADC.
V
DDA
Analog positive power supply I N/A V
DDA
Power 496
324
V
SSA
Analog negative power supply I N/A V
SSA
Power 496
324
1
Terminology is O — output, I — input, Up — weak pullup enabled, Down — weak pulldown enabled, Low — output driven
low, High — output driven high. A dash on the left side of the slash denotes that both the input and output buffers for the
pin are off. A dash on the right side of the slash denotes that there is no weak pullup/down enabled on the pin. The signal
name to the left or right of the slash indicates the pin is enabled.
2
Function after reset of GPI is general-purpose input. A dash on the left side of the slash denotes that both the input and
output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pullup/down enabled
on the pin.
Table 18-2. eQADC Memory Map
Address Register Name Register Description Bits
Base (0xFFF8_0000) EQADC_MCR EQADC module configuration register 32
Base + 0x004 — Reserved —
Base + 0x008 EQADC_NMSFR eQADC null message send format register 32
Base + 0x00C EQADC_ETDFR eQADC external trigger digital filter register 32
Base + 0x010 EQADC_CFPR0 eQADC command FIFO push register 0 32
Base + 0x014 EQADC_CFPR1 eQADC command FIFO push register 1 32
Base + 0x018 EQADC_CFPR2 eQADC command FIFO push register 2 32
Base + 0x01C EQADC_CFPR3 eQADC command FIFO push register 3 32
Base + 0x020 EQADC_CFPR4 eQADC command FIFO push register 4 32
Base + 0x024 EQADC_CFPR5 eQADC command FIFO push register 5 32
Base + 0x028 — Reserved —
Base + 0x02C — Reserved —
Base + 0x030 EQADC_RFPR0 eQADC result FIFO pop register 0 32
Table 18-1. eQADC External Signals (continued)
Function Description
I/O
Type
Status
During
Reset
1
Status
After
Reset
2
Type Package