Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 17-41
17.4.6.3 eTPU Channel n Status Control Register (ETPU_C n SCR)
ETPU_C n SCR is a collection of the interrupt status bits of the channel, and also the function mode
definition (read-write). Bits CIS, CIOS, DTRS, and DTROS for each channel can also be accessed from
ETPU_CISR, ETPU_CIOSR, ETPU_CDTRSR, and ETPU_CDTROSR respectively. For more
information on the three previously mentioned registers, refer to the
eTPU Reference Manual .
NOTE
The device core must write 1 to clear a status bit.
NOTE
In the MPC5565, eTPU A channels [0:2, 14:15] are DMA connected. The
data transfer request lines that are not connected to the DMA controller are
left disconnected and do not generate transfer requests, even if their request
status bits assert in registers ETPU_CDTRSR and ETPU_C
n SCR
18–20 Reserved.
21–31
CPBA
[0:10]
Channel n parameter base address. The value of this field multiplied by 8 specifies the SDM parameter base host
(byte) address for channel n (2-parameter granularity).
The formula for calculating the absolute channel parameter base (byte) address, as seen by the host, is eTPU_Base
+ CPBA*8. The SDM is mirrored in the parameter sign extension (PSE) area. The formula to calculate the
absolute channel parameter base (byte) address in the PSE area is eTP CPBA*8.
For more information on SDM addresses, refer to the
eTPU Reference Manual .
Address: Channel_Registe 0x0004 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CIS CIOS 0 0 0 0 0 0 DTRS DTROS 0 0 0 0 0 0
W w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R IPS OPS 0 0 0 0 0 0 0 0 0 0 0 0
FM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-23. eTPU Channel n Status Control Register (ETPU_C n SCR)
Table 17-25. ETPU_C n CR Field Descriptions (continued)
Field Description