Freescale Semiconductor MPC5565, Reference Manual

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Introduction
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 1-13
1.4.4 Interrupt Controller (INTC)
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests,
suitable for statically scheduled real-time systems. The INTC allows interrupt request servicing from 231
total interrupt vectors.
For high-priority interrupt requests, the time from when the peripheral interrupt request asserts to when
the processor executes the interrupt service routine (ISR) is minimized. A unique vector for each interrupt
request source is used to quickly determine which ISR to execute. The INTC module provides a number
of priorities to ensure that lower priority ISRs do not delay the execution of higher priority ISRs. Software
is used to configure the interrupt priorities for each interrupt source.
When multiple tasks share a resource, coherent accesses to that resource must be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority level can be raised temporarily so that no task can preempt another task that shares the same
resource.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests
(by using application software to assert requests). These maskable interrupt requests can divide the
software into a high-priority portion and a low-priority portion for servicing the interrupt requests. The
high-priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a software
settable interrupt request to finish the servicing in a lower priority ISR.
1.4.5 Frequency Modulated Phase-Locking Loop (FMPLL)
The frequency modulated phase-locking loop (FMPLL) generates high-speed system clocks from an
8–20 MHz crystal oscillator or an external clock generator. Furthermore, the FMPLL supports
programmable frequency modulation of the system clock. The PLL multiplication factor, output clock
divider ratio, modulation depth, and modulation rate are all software configurable.
1.4.6 External Bus Interface (EBI)
The external bus interface (EBI) controls data transfer across the crossbar switch to/from memories or
peripherals in the external address space. The EBI is available on the 324 BGA package only. The EBI also
enables an external master to access internal address space. The EBI includes a memory controller that
generates interface signals to support a variety of external memories. The memory controller supports
single data rate (SDR) burst mode flash, external SRAM, and asynchronous memories. In addition, the
EBI supports up to four regions (via chip selects), along with programmed region-specific attributes.
1.4.7 Calibration Bus Interface (CBI)
The calibration bus controls data transfer across the crossbar switch to/from memories or peripherals
connected to the
VertiCal connector. The calibration bus is only available when the silicon is packaged in
the VertiCal calibration assembly. The bus shares the memory controller and most of the control logic with
the EBI but the two buses use separate pads. The calibration bus memory controller supports single data
rate (SDR) non-burst mode flash, SRAM, and asynchronous memories. In addition, the bus supports up to