Freescale Semiconductor MPC5565, Reference Manual

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Interrupt Controller (INTC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 10-11
10.3.1.3 INTC Interrupt Acknowledge Register (INTC_IACKR)
The INTC_IACKR provides a value that can be used to load the address of an ISR from a vector table. The
vector table can be composed of addresses of the ISRs specific to their respective interrupt vectors.
In software vector mode, reading the INTC_IACKR acknowledges the INTC's interrupt request. Refer to
Section 10.1.4.1, “Software Vector Mode ” for a detailed description of the effect on the interrupt request
to the processor. The reading also pushes the PRI value in the INTC current priority register (INTC_CPR)
onto the LIFO and updates PRI in the INTC_CPR with the priority of the interrupt request. The side effect
from the reads in software vector mode, that is, the effect on the interrupt request to the processor, the
current priority, and the LIFO, are the same regardless of the size of the read
Reading the INTC_IACKR does not have side effects in hardware vector mode.
NOTE
The INTC_IACKR must not be read speculatively while in software vector
mode. Therefore, for future compatibility, the TLB entry covering the
INTC_IACKR must be configured to be guarded.
In software vector mode, the INTC_IACKR must be read before setting
MSR[EE]. No synchronization instruction is needed after reading the
INTC_IACKR and before setting MSR[EE].
However, the time for the processor to recognize the assertion or negation
of the external input to it is not defined by the book E architecture and can
be greater than 0. Therefore, insert instructions between the reading of the
INTC_IACKR and the setting of MSR[EE] that consumes at least two
processor clock cycles. This length of time allows the interrupt request
negation to propagate through the processor before MSR[EE] is set.
Table 10-5. INTC_CPR Field Descriptions
Field Description
0–27 Reserved, must be cleared.
28–31
PRI
Priority. PRI is the priority of the currently executing ISR according to the field values defined below.
1111 Priority 15 (highest)
1110 Priority 14
...
0001 Priority 1
0000 Priority 0 (lowest)
Address: Base + 0x0010 (INTC_IACKR) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
VTBA
INTVEC 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 10-9. INTC Interrupt Acknowledge Register (INTC_IACKR)—INTC_MCR[VTES] = 0