Freescale Semiconductor MPC5565, Reference Manual

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Interrupt Controller (INTC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
10-4 Freescale Semiconductor
For high priority interrupt requests in these target applications, the time from the assertion of the interrupt
request from the peripheral to when the processor is performing useful work to service the interrupt request
needs to be minimized. The INTC can be optimized to support this goal through the hardware vector mode,
where a unique vector is provided for each interrupt request source. It also provides 16 priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. Since each individual application
has different priorities for each source of interrupt request, the priority of each interrupt request is
configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority level can be raised temporarily so that no task can preempt another task that shares the same
resource.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests,
i.e., by using application software to assert an interrupt request. These same software settable interrupt
requests also can be used to break the work involved in servicing an interrupt request into a high priority
portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request,
but then the ISR can assert a software settable interrupt request to finish the servicing in a lower priority
ISR.
10.1.3 Features
Features include the following:
• Total number of interrupt vectors is 232
1
, of which
— 8 are software settable sources, and
— 16 are reserved sources.
• 9-bit unique vector for each interrupt request source in hardware vector mode.
• Each interrupt source can be programmed to one of 16 priorities.
• Preemption.
— Preemptive prioritized interrupt requests to processor.
— ISR at a higher priority preempts ISRs or tasks at lower priorities.
— Automatic pushing or popping of preempted priority to or from a LIFO.
— Ability to modify the ISR or task priority. Modifying the priority can be used to implement the
priority ceiling protocol for accessing shared resources.
• Low latency–three clocks from receipt of interrupt request from peripheral to interrupt request to
processor.
10.1.4 Modes of Operation
The interrupt controller has two handshaking modes with the processor: software vector mode and
hardware vector mode. The state of the hardware vector enable bit, INTC_MCR[HVEN], determines
which mode is used.
1. Although N (maximum number of addressable IRQ vectors) = 231, the total number of interrupts must be a multiple of four.
Therefore, the total number of interrupts is 232: 208 peripheral IRQs, 8 software-configurable IRQs, and 16 reserved.