Freescale Semiconductor MPC5565, Reference Manual

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Crossbar Switch (XBAR)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
7-2 Freescale Semiconductor
7.1.2 Overview
The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible
for all master ports and slave ports to be in use at the same time as a result of independent master requests.
If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grant it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions.
By default, requesting masters are granted access based on a fixed priority. A round-robin priority mode
also is available. In this mode, requesting masters are treated with equal priority and are granted access to
a slave port in round-robin fashion, based upon the ID of the last master to be granted access. A block
diagram of the XBAR is shown in
Figure 7-1 .
The XBAR can place a slave port in a low-power park mode to avoid dissipating any power transitional
address, control or data signals when the master port is not actively accessing the slave port. There is a
one-cycle arbitration overhead for exiting low-power park mode.
7.1.3 Features
• Three master ports:
— core: e200z6 core and Nexus
— eDMA
— EBI
• Five slave ports
— Flash (refer to Chapter 13, “Flash Memory ” for information on accessing flash memory)
— EBI
— Internal SRAM
— Peripheral bridge A
— Peripheral bridge B
• 32-bit address, 64-bit data paths
• Fully concurrent transfers between independent master and slave ports
External bus interface Slave 1 —
Internal SRAM Slave 3 —
Peripheral bridge A (PBRIDGE_A) Slave 6 —
Peripheral bridge B (PBRIDGE_B) Slave 7 —
Table 7-1. XBAR Switch Ports (continued)
Module
Port
Master ID
Type Number