Freescale Semiconductor MPC5565, Reference Manual

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e200z6 Core Complex
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 3-11
3.2.2 Core-Specific Registers
The Power Architecture embedded category allows implementation-specific registers.
Implementation-specific registers incorporated in the e200z6 core are described in this section.
3.2.2.1 User-Level Registers
The user-level registers can be accessed by all software with either user or supervisor privileges. They
include the following:
• Signal processing extension APU status and control register (SPEFSCR). The SPEFSCR contains
all fixed-point and floating-point exception signal bits, exception summary bits, exception enable
bits, and rounding control bits needed for compliance with the IEEE 754 standard.
• The L1 cache configuration register (L1CFG0). This read-only register allows software to query
the configuration of the L1 unified cache.
3.2.2.2 Supervisor-Level Registers
The following supervisor-level registers are defined in the e200z6 core in addition to the Power
Architecture embedded category registers described previously:
• Configuration registers
— Hardware implementation-dependent 0 (HID0) controls processor and system functions.
— Hardware implementation-dependent 1 (HID1) controls processor and system functions.
• Exception handling and control registers
— Debug save and restore registers (DSRR0, DSRR1). DSRR0 holds the effective address for the
instruction at which execution resumes when an rfdi instruction is executed at the end of a
debug interrupt handler routine. DSRR1 is used to save machine state on a debug interrupt, and
stores the MSR register contents. The MSR value is restored when an
rfdi instruction is
executed at the end of a debug interrupt handler routine.
— When enabled, the DSRR0 register is used to save the address of the instruction at which
execution continues when rfdi executes at the end of a debug interrupt handler routine.
— Interrupt vector offset registers (IVOR32–IVOR34). These registers provide the address of the
interrupt handler for different classes of interrupts.
• Debug facility registers
— Debug control register 3 (DBCR3) controls for debug functions not described in the
Power Architecture embedded category.
— Debug counter register (DBCNT) provides counter capability for debug functions.
• Cache registers
— L1 cache configuration register (L1CFG0) is a read-only register that allows software to query
the configuration of the L1 cache.
— L1 cache control and status register (L1CSR0) controls the operation of the L1 unified cache
such as cache enabling, cache invalidation, cache locking, etc.