Calibration
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
B-5
B.4.2
Pad Ring
This section provides a list of the calibration pins and associated pad configuration registers (PCRs),
including links to the detailed PCR information for each pin or pin group.
Refer to
for device signal names.
The drive strength of the calibration pins is configured in the PCR registers. In some cases, multiple pads
have their drive strengths controlled by one PCR by grouping the pins:
•
CAL_ADDR[12:30]
•
CAL_DATA[0:15]
•
CAL_RD_WR, CAL_WE/BE[0:1], CAL_OE, CAL_TS
The SIU_PCR registers control whether the CAL_CS[2:3] pins are used for CAL_CS[2:3] or for
CAL_ADDR[10:11]. Refer to
for the pin assignments. Selecting between CAL_CS[2:3] and
CAL_ADDR[10:11] allows you to maximize the amount of calibration memory size by limiting the
number of calibration chip selects to CS[0]. Refer to
Section B.4.1.1, “Number of Chip Selects and
B.4.3
CLKOUT
CLKOUT is supplied by the clock control block, not the EBI. Nevertheless, the same CLKOUT is used
for both the non-calibration and calibration bus.
A drawback of having just one CLKOUT is that while the difference in board timing can be compensated
by the adjustment in the drive strength, the CLKOUT timing, and hence the timing of the non-calibration
bus, can have minor differences with a calibration tool from the production package.
B.5
Power Supplies
The signals that make up the calibration bus have their own power supply segment (V
DDE12
). The V
DDE12
power supply balls are not connected to any other power supply segment from the standard package
ball-out but are routed on the VertiCal base to pins on the VertiCal connector. The VertiCal top board must
provide voltage to the V
DDE12
power supply pins to power up the calibration bus. The VertiCal top board
can derive a 3.3 V supply by regulating down the vehicle battery voltage, connected via a connector and
flying lead to the top board.
B.6
Integration Logic Functionality
The EBI connects to both the non-calibration and calibration buses. The integration logic on MPC5565
selects between the data input from both buses to the EBI.
The MPC5565 integration logic also suppresses the reflections of the outputs of the calibration bus onto
the non-calibration bus. For the non-calibration bus pins that do not have a negated state to which the pins
return at the end of the access, this reflection suppression is enabled by the SIU_CCR[CRSE] bit.
SIU_CCR[CRSE] does not enable reflection suppression for the non-calibration bus pins that have a
negated state to which the pins return at the end of an access. Those reflections always are suppressed.
Summary of Contents for MPC5565
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Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
