Freescale Semiconductor MPC5565, Reference Manual

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e200z6 Core Complex
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 3-3
processing unit (APU) is provided to support real-time fixed point and single-precision floating point
operations using the general-purpose registers. All arithmetic instructions that execute in the core operate
on data in the GPRs. The registers have been extended to 64-bits to support vector instructions defined by
the SPE APU. These instructions operate on 16-bit or 32-bit data types, and produce vector or scalar
results.
In addition to the base Power Architecture instruction set, the e200z6 core also implements the VLE
(Variable Length Encoding) APU, providing improved code density.
3.1.3 Features
The following is a list of some key features of the e200z6:
• Single issue, 32-bit CPU built on the Power Architecture embedded category
• Implements the VLE APU for reduced code footprint. Refer to EREF: A Programmer's Reference
Manual for Freescale Book E Processors and to VLEPIM: Variable Length Encoding (VLE)
Extension Programming Interface Manual .
• In-order execution and retirement
• Precise exception handling
• Branch target address cache
— Dedicated branch address calculation adder
— Branch target prefetching
— Branch lookahead buffers of depth 2
• Load/store unit
— Pipelined operation supports throughput of one load or store operation per cycle
• 64-bit general-purpose register file
• Memory management unit (MMU) with 32-entry fully-associative TLB and multiple page size
support
• Eight KB, two-way set associative unified cache
• Periodic timer and watchdog functions
• Periodic system integrity can be monitored through parallel signature checks
• Signal processing extension APU supporting fixed-point and single-precision floating-point
operations, using the 64-bit general-purpose register file
• Nexus class 3 real-time development unit
• Power management
— Low-power design
— Dynamic power management of execution units, caches, and MMUs