Nexus
MPC5565 Microcontroller Reference Manual, Rev. 1.0
24-26
Freescale Semiconductor
24.7.2.8
Nexus Reset Control
The JCOMP input that is used as the primary reset signal for the NPC is also used by the NPC to generate
a single-bit reset signal for other Nexus modules. If JCOMP is negated, an internal reset signal is asserted,
indicating that all Nexus modules should be held in reset. This internal reset signal is also asserted during
a power-on reset, or if nex_disable is asserted (SIU_CCR[DISNEX]), indicating the device is in censored
mode. This single bit reset signal functions much like the IEEE
®
1149.1-2001 defined TRST signal and
allows JCOMP reset information to be provided to the Nexus modules without each module having to
sense the JCOMP signal directly or monitor the status of censored mode.
24.8
NPC Initialization/Application Information
24.8.1
Accessing NPC Tool-Mapped Registers
To initialize the TAP for NPC register accesses, the following sequence is required:
1. Enable the NPC TAP controller. This is achieved by asserting JCOMP and loading the
ACCESS_AUX_TAP_NPC instruction in the JTAGC.
2. Load the TAP controller with the NEXUS-ENABLE instruction.
To write control data to NPC tool-mapped registers, the following sequence is required:
1. Write the 7-bit register index and set the write bit to select the register with a pass through the
SELECT-DR-SCAN path in the TAP controller state machine.
2. Write the register value with a second pass through the SELECT-DR-SCAN path. Note that the
prior value of this register is shifted out during the write.
To read status and control data from NPC tool-mapped registers, the following sequence is required:
1. Write the 7-bit register index and clear the write bit to select register with a pass through
SELECT-DR-SCAN path in the TAP controller state machine.
2. Read the register value with a second pass through the SELECT-DR-SCAN path. Data shifted in
is ignored.
Refer to the IEEE
®
-ISTO 5001-2003 standard for more detail.
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
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Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...