Freescale Semiconductor MPC5553, Reference Manual

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
3-20 Freescale Semiconductor
3.3.2 L1 Cache
The e200z6 processor supports a 32-kilobyte, 8-way set-associative, unified (instruction and data) cache
with a 32-byte line size in the MPC5554; the MPC5553 provides an 8-Kbyte, 2-way set associative unified
cache with a 32-byte line size. The cache improves system performance by providing low-latency data to
the e200z6 instruction and data pipelines, which decouples processor performance from system memory
performance. The cache is virtually indexed and physically tagged. The e200z6 does not provide hardware
support for cache coherency in a multi-master environment. Software must be used to maintain cache
coherency with other possible bus masters.
Both instruction and data accesses are performed using a single bus connected to the cache. Addresses
from the processor to the cache are virtual addresses used to index the cache array. The MMU provides the
virtual to physical translation for use in performing the cache tag compare. If the physical address matches
a valid cache tag entry, the access hits in the cache. For a read operation, the cache supplies the data to the
processor, and for a write operation, the data from the processor updates the cache. If the access does not
match a valid cache tag entry (misses in the cache) or a write access must be written through to memory,
the cache performs a bus cycle on the system bus.
Figure 3-13 shows a block diagram of the unified cache
in the e200z6.
Table 3-8. MAS6—TLB Search Context Register 0
Bits Name Description
0–7 — Reserved, should be cleared.
8–15 SPID PID value for searches
16–30 — Reserved, should be cleared.
31 SAS AS value for searches