3.5.2 Flash Memory Controller Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Register
access
Flash memory
controller
Transfers
Peripheral bus
controller 0
Transfers
Flash
memory
Crossbar
switch
Figure 3-21. Flash memory controller configuration
Table 3-32. Reference links to related information
Topic
Related module
Reference
Full description
Flash memory
controller
System memory map
Clocking
Transfers
Flash memory
Transfers
Crossbar switch
Register access
Peripheral bridge
3.5.2.1 Number of masters
The Flash Memory Controller supports up to eight crossbar switch masters. However,
this device has a different number of crossbar switch masters. See
for details on the master port assignments.
3.5.3 SRAM Configuration
This section summarizes how the module has been configured in the chip.
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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