Table 35-79. Modes of DAC data buffer operation (continued)
Modes
Description
FIFO Mode
In FIFO mode, the buffer is organized as a FIFO. For a valid
write to any DACDATx, the data is put into the FIFO, and the
write pointer is automatically incremented. The module is
connected internally to a 32bit interface. For any 16bit or 8bit
FIFO access, address bit[1] needs to be 0; otherwise, the
write is ignored. For any 32bit FIFO access, the Write_Pointer
needs to be an EVEN number; otherwise, the write is ignored.
NOTE: A successful 32bit FIFO write will increase the write
pointer by 2. Any write will cause the FIFO over-flow
will be ignored, the cases includes: 1.FIFO is full, the
write will be ignored. 2.FIFO is nearly full
(FIFO_SIZE-1), 32bit write will be ignored.
NOTE: For 8bit write, address bit[0] determine which byte
lane will be written to the FIFO according to little
endian alignment. Only both byte lanes are written
will the write pointer increase. User need to make
sure 8bit access happened in pair and both upper &
lower bytes are written. There is no requirement on
which byte write first. In FIFO mode, there is no
change to read access of DACDATx (from normal
mode), read to DACDATx will return the DATA
addressed by the access address to the data buffer,
and both write pointer and read pointer in FIFO mode
will NOT be changed by read access. FIFO write can
be happened when DAC is not enabled for 1st data
conversion enable. But FIFO mode need to work at
buffer Enabled at DACC1[DACBFEN].
In FIFO mode, the DATA BUF will be organized as FIFO.
35.5.2 DMA operation
When DMA is enabled, DMA requests are generated instead of interrupt requests. The
DMA Done signal clears the DMA request.
The status register flags are still set and are cleared automatically when the DMA
completes.
35.5.3 Resets
During reset, the DAC is configured in the default mode and is disabled.
Functional description
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
782
Freescale Semiconductor, Inc.
