FMC_PFB0CR field descriptions (continued)
Field
Description
0
Do not cache instruction fetches.
1
Cache instruction fetches.
2
B0DPE
Bank 0 Data Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to data references.
0
Do not prefetch in response to data references.
1
Enable prefetches in response to data references.
1
B0IPE
Bank 0 Instruction Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction
fetches.
0
Do not prefetch in response to instruction fetches.
1
Enable prefetches in response to instruction fetches.
0
B0SEBE
Bank 0 Single Entry Buffer Enable
This bit controls whether the single entry page buffer is enabled in response to flash read accesses. Its
operation is independent from bank 1's cache.
A high-to-low transition of this enable forces the page buffer to be invalidated.
0
Single entry buffer is disabled.
1
Single entry buffer is enabled.
Chapter 28 Flash Memory Controller (FMC)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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