SIM_SOPT2 field descriptions (continued)
Field
Description
01
MCGFLLCLK , or MCGPLLCLK, or IRC48M clock as selected by SOPT2[PLLFLLSEL].
10
OSCERCLK clock
11
MCGIRCLK clock
25–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–22
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18
USBSRC
USB clock source select
Selects the clock source for the USB 48 MHz clock.
0
External bypass clock (USB_CLKIN).
1
MCGFLLCLK, or MCGPLLCLK, or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then
divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].
17–16
PLLFLLSEL
PLL/FLL clock select
Selects the high frequency clock for various peripheral clocking options.
00
MCGFLLCLK clock
01
MCGPLLCLK clock
10
Reserved
11
IRC48 MHz clock
15–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
TRACECLKSEL
Debug trace clock select
Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace clock source.
0
MCGOUTCLK
1
Core/system clock
11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–5
CLKOUTSEL
CLKOUT select
Selects the clock to output on the CLKOUT pin.
000
Reserved
001
Reserved
010
Flash clock
011
LPO clock (1 kHz)
100
MCGIRCLK
101
RTC 32.768kHz clock
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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