44.4.7.1 End Of Queue interrupt request
The End Of Queue (EOQ) interrupt request indicates that the end of a transmit queue is
reached. The module generates the interrupt request when EOQ interrupt requests are
enabled (RSER[EOQF_RE]) and the EOQ bit in the executing SPI command is 1.
The module generates the interrupt request when the last bit of the SPI frame with EOQ
bit set is transmitted.
44.4.7.2 Transmit FIFO Fill Interrupt or DMA Request
The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit
FIFO Fill Request is generated when the number of entries in the TX FIFO is less than
the maximum number of possible entries, and the TFFF_RE bit in the RSER is set. The
TFFF_DIRS bit in the RSER selects whether a DMA request or an interrupt request is
generated.
NOTE
TFFF flag clears automatically when DMA is used to fill TX
FIFO.
To clear TFFF when not using DMA, follow these steps for
every PUSH performed using CPU to fill TX FIFO:
1. Wait until TFFF = 1.
2. Write data to PUSHR using CPU.
3. Clear TFFF by writing a 1 to its location. If TX FIFO is not
full, this flag will not clear.
44.4.7.3 Transfer Complete Interrupt Request
The Transfer Complete Request indicates the end of the transfer of a serial frame. The
Transfer Complete Request is generated at the end of each frame transfer when the
TCF_RE bit is set in the RSER.
44.4.7.4 Transmit FIFO Underflow Interrupt Request
The Transmit FIFO Underflow Request indicates that an underflow condition in the TX
FIFO has occurred. The transmit underflow condition is detected only for the module
operating in Slave mode and SPI configuration . The TFUF bit is set when the TX FIFO
Functional description
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1086
Freescale Semiconductor, Inc.
