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Freescale Semiconductor MCF54455, Reference Manual

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Cache

6-16

Freescale Semiconductor

6.4.3

Cache Coherency (Data Cache Only)

The processor provides limited support for maintaining cache coherency in multiple-master environments. 
Write-through and copyback memory update techniques are supported to maintain coherency between the 
cache and memory.

The cache does not support snooping (cache coherency is not supported while external or DMA masters 
use the bus). Therefore, on-chip DMA channels should not access cached local memory locations because 
coherency is not maintained with the data cache.

6.4.4

Memory Accesses for Cache Maintenance

The cache controller performs all maintenance activities that supply data from the cache to the core, 
including requests for reading new cache lines and writing modified cache lines to memory. The following 
sections describe memory accesses resulting from cache fill and push operations.

6.4.4.1

Cache Filling

When a new cache line is required, a line read is requested, which generates a burst-read transfer by 
indicating a line access with the size signals, SIZ[1:0].

The responding device supplies four consecutive longwords of data. Line accesses implicitly request 
burst-mode operations from memory, but burst operations can be inhibited or enabled through the burst 
read/write enable bits (CSCR

n

[BSTR, BSTW]). For more information regarding external bus burst-mode 

accesses, see 

Chapter 20, “FlexBus.”

The first cycle of a cache-line read loads the longword entry corresponding to the requested address. 
Subsequent transfers load the remaining longword entries.

A burst operation aborts by a write-protection fault, which is the only possible access error. Exception 
processing proceeds immediately. Unlike Version 2 and Version 3 access errors, the program counter 
stored on the exception stack frame points to the faulting instruction. See 

Section 3.3.4.1, “Access Error 

Exception.”

6.4.4.2

Cache Pushes

Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction. To 
reduce the requested data’s latency in the new line, the modified line being replaced is temporarily placed 
in the push buffer while the new line is fetched from memory. After the bus transfer for the new line 
completes, the modified cache line writes back to memory and the push buffer invalidates.

6.4.4.2.1

Push and Store Buffers

The 16-byte push buffer reduces latency for requested new data on a cache miss by holding a displaced 
modified data cache line while the new data is read from memory. 

If a cache miss displaces a modified line, a miss read reference is immediately generated. While waiting 
for the response, the current contents of the cache location load into the push buffer. When the burst-read 

Summary of Contents for MCF54455

Page 1: ...reescale Semiconductor MCF54455RM Rev 6 1 03 2012 This is the MCF54455 Reference Manual set consisting of the following files MCF54455 Reference Manual Errata Rev 1 MCF54455 Reference Manual Rev 6 MCF54455 Reference Manual by Microcontroller Solutions Group ...

Page 2: ...tions to the MCF54455 Reference Manual order number MC54455RM For convenience the addenda items are grouped by revision Please check our website at http www freescale com for the latest updates The current available version of the MCF54455 Reference Manual is Revision 6 MCF54455 Reference Manual Errata by Microcontroller Solutions Group 1 Errata for Revision 6 2 2 Revision History 2 ...

Page 3: ...y for this document Table 1 MCF54455 Reference Manual Rev 6 Errata Location Description Section 16 2 External Signal Description Table 16 2 Page 16 11 Add pin N7 to the VSS pin list for the 360 TEPBGA Table 2 Revision History Table Rev Number Substantive Changes Date of Release 1 0 Initial release Correct errors in section 16 2 External Signal Description 11 2011 ...

Page 4: ...MCF54455 Reference Manual Errata Rev 1 Freescale Semiconductor 3 THIS PAGE IS INTENTIONALLY LEFT BLANK ...

Page 5: ...e application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be va...

Page 6: ...MCF54455 Reference Manual Devices Supported MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455 Document Number MCF54455RM Rev 6 5 2011 ...

Page 7: ...oes Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may var...

Page 8: ...agement 1 5 1 6 5 Chip Configuration Module CCM 1 5 1 6 6 Reset Controller 1 6 1 6 7 System Control Module 1 6 1 6 8 Crossbar Switch 1 6 1 6 9 Peripheral Component Interconnect PCI Bus 1 6 1 6 10 Universal Serial Bus USB 2 0 On The Go OTG Controller 1 6 1 6 11 DDR SDRAM Controller 1 6 1 6 12 FlexBus External Interface 1 7 1 6 13 Synchronous Serial Interface SSI 1 7 1 6 14 ATA Controller 1 7 1 6 15...

Page 9: ...10 2 3 4 FlexBus Signals 2 11 2 3 5 SDRAM Controller Signals 2 12 2 3 6 PCI Controller Signals 2 13 2 3 7 Serial Boot Facility Signals 2 14 2 3 8 External Interrupt Signals 2 14 2 3 9 DMA Signals 2 14 2 3 10 Fast Ethernet Controller FEC0 and FEC1 Signals 2 14 2 3 11 I2C I O Signals 2 15 2 3 12 ATA Controller Signals 2 16 2 3 13 DMA Serial Peripheral Interface DSPI Signals 2 17 2 3 14 Synchronous S...

Page 10: ... Timing 3 27 Chapter 4 Memory Management Unit MMU 4 1 Introduction 4 1 4 1 1 Block Diagram 4 1 4 1 2 Features 4 2 4 2 Memory Map Register Definition 4 3 4 2 1 Address Space ID ASID 4 4 4 2 2 MMU Base Address Register MMUBAR 4 4 4 2 3 MMU Control Register MMUCR 4 5 4 2 4 MMU Operation Register MMUOR 4 6 4 2 5 MMU Status Register MMUSR 4 7 4 2 6 MMU Fault Test or TLB Address Register MMUAR 4 8 4 2 7...

Page 11: ... 5 15 Chapter 6 Cache 6 1 Introduction 6 1 6 1 1 Block Diagram 6 1 6 1 2 Overview 6 1 6 2 Cache Organization 6 2 6 2 1 Cache Line States Invalid Valid Unmodified and Valid Modified 6 3 6 2 2 The Cache at Start Up 6 3 6 3 Memory Map Register Definition 6 5 6 3 1 Cache Control Register CACR 6 5 6 3 2 Access Control Registers ACRn 6 8 6 4 Functional Description 6 9 6 4 1 Caching Modes 6 12 6 4 2 Cach...

Page 12: ...iplication Factor Select 8 9 8 3 2 Lock Conditions 8 10 8 3 3 Loss of Lock 8 10 8 3 4 System Clock Modes 8 11 8 3 5 Clock Operation During Reset 8 12 Chapter 9 Power Management 9 1 Introduction 9 1 9 1 1 Features 9 1 9 2 Memory Map Register Definition 9 1 9 2 1 Wake up Control Register WCR 9 2 9 2 2 Peripheral Power Management Set Register PPMSR0 9 3 9 2 3 Peripheral Power Management Clear Registe...

Page 13: ... PHY Interface 10 47 10 5 Initialization Application Information 10 48 10 5 1 Host Operation 10 48 10 5 2 Device Data Structures 10 49 10 5 3 Device Operation 10 56 10 5 4 Servicing Interrupts 10 74 10 5 5 Deviations from the EHCI Specifications 10 75 Chapter 11 Chip Configuration Module CCM 11 1 Introduction 11 1 11 1 1 Block Diagram 11 1 11 1 2 Features 11 1 11 1 3 Modes of Operation 11 1 11 2 E...

Page 14: ...Shift Clock Frequency Adjustment 12 4 12 4 2 Reset Configuration and Optional Boot Load 12 5 12 4 3 Execution Transfer 12 6 12 5 Initialization Information 12 6 12 5 1 SPI Memory Initialization 12 6 12 5 2 FAST_READ Feature Initialization 12 7 Chapter 13 Reset Controller Module 13 1 Introduction 13 1 13 1 1 Block Diagram 13 1 13 1 2 Features 13 1 13 2 External Signal Description 13 2 13 2 1 RESET ...

Page 15: ...ional Description 14 13 14 3 1 Access Control 14 13 14 3 2 Core Watchdog Timer 14 13 14 3 3 Core Data Fault Recovery Registers 14 14 Chapter 15 Crossbar Switch XBS 15 1 Overview 15 1 15 2 Features 15 3 15 3 Modes of Operation 15 3 15 4 Memory Map Register Definition 15 3 15 4 1 XBS Priority Registers XBS_PRSn 15 4 15 4 2 XBS Control Registers XBS_CRSn 15 5 15 5 Functional Description 15 7 15 5 1 A...

Page 16: ...Register SIMRn 17 8 17 2 6 Clear Interrupt Mask Register CIMRn 17 9 17 2 7 Current Level Mask Register CLMASK 17 9 17 2 8 Saved Level Mask Register SLMASK 17 10 17 2 9 Interrupt Control Register ICR0n ICR1n n 00 01 02 63 17 11 17 2 10 Software and Level 1 7 IACK Registers SWIACKn L1IACKn L7IACKn 17 15 17 3 Functional Description 17 16 17 3 1 Interrupt Controller Theory of Operation 17 16 17 3 2 Pr...

Page 17: ...gister EDMA_SEEI 19 11 19 4 8 eDMA Clear Enable Error Interrupt Register EDMA_CEEI 19 11 19 4 9 eDMA Clear Interrupt Request Register EDMA_CINT 19 12 19 4 10 eDMA Clear Error Register EDMA_CERR 19 13 19 4 11 eDMA Set START Bit Register EDMA_SSRT 19 13 19 4 12 eDMA Clear DONE Status Bit Register EDMA_CDNE 19 14 19 4 13 eDMA Interrupt Request Register EDMA_INT 19 15 19 4 14 eDMA Error Register EDMA_...

Page 18: ... Select Mask Registers CSMR0 CSMR5 20 7 20 3 3 Chip Select Control Registers CSCR0 CSCR5 20 7 20 4 Functional Description 20 10 20 4 1 Chip Select Operation 20 10 20 4 2 Data Transfer Operation 20 11 20 4 3 Data Byte Alignment and Physical Connections 20 12 20 4 4 Address Data Bus Multiplexing 20 12 20 4 5 Bus Cycle Execution 20 13 20 4 6 FlexBus Timing Examples 20 14 20 4 7 Burst Cycles 20 26 20 ...

Page 19: ...2 PCI Bus Controller 22 1 Introduction 22 1 22 1 1 Block Diagram 22 1 22 1 2 Overview 22 1 22 1 3 Features 22 2 22 1 4 Modes of Operation 22 2 22 2 External Signal Description 22 3 22 2 1 Address Data Bus PCI_AD 31 0 22 3 22 2 2 Clock PCI_CLK 22 3 22 2 3 Command Byte Enables PCI_CBE 3 0 22 3 22 2 4 Device Select PCI_DEVSEL 22 4 22 2 5 Frame PCI_FRAME 22 4 22 2 6 Grant PCI_GNT 3 0 22 4 22 2 7 Initi...

Page 20: ...odes of Operation 23 2 23 2 External Signal Description 23 3 23 2 1 Detailed Signal Descriptions 23 4 23 3 Memory Map Register Definition 23 5 23 3 1 Endianness 23 6 23 3 2 Timing Registers TIME_x 23 7 23 3 3 FIFO Data Register FIFO_DATA_n 23 7 23 3 4 FIFO_FILL Register 23 8 23 3 5 ATA Control Register ATA_CR 23 8 23 3 6 Interrupt Registers 23 9 23 3 7 FIFO Alarm Register FIFO_ALARM 23 12 23 3 8 D...

Page 21: ... 25 1 1 Overview 25 1 25 2 Memory Map Register Definition 25 2 25 2 1 RNG Control Register RNGCR 25 2 25 2 2 RNG Status Register RNGSR 25 3 25 2 3 RNG Entropy Register RNGER 25 4 25 2 4 RNG Output FIFO RNGOUT 25 4 25 3 Functional Description 25 5 25 3 1 Output FIFO 25 5 25 3 2 RNG Core Control Logic Block 25 5 25 4 Initialization Application Information 25 6 Chapter 26 Fast Ethernet Controllers FE...

Page 22: ...ters GAUR0 GAUR1 26 24 26 4 18 Descriptor Group Lower Address Registers GALR0 GALR1 26 25 26 4 19 Transmit FIFO Watermark Registers TFWR0 TFWR1 26 25 26 4 20 FIFO Receive Bound Registers FRBR0 FRBR1 26 26 26 4 21 FIFO Receive Start Registers FRSR0 FRSR1 26 26 26 4 22 Receive Descriptor Ring Start Registers ERDSR0 ERDSR1 26 27 26 4 23 Transmit Buffer Descriptor Ring Start Registers ETSDR0 ETSDR1 26...

Page 23: ...CR 27 13 27 3 8 SSI Interrupt Status Register SSI_ISR 27 15 27 3 9 SSI Interrupt Enable Register SSI_IER 27 20 27 3 10 SSI Transmit Configuration Register SSI_TCR 27 21 27 3 11 SSI Receive Configuration Register SSI_RCR 27 23 27 3 12 SSI Clock Control Register SSI_CCR 27 24 27 3 13 SSI FIFO Control Status Register SSI_FCSR 27 25 27 3 14 SSI AC97 Control Register SSI_ACR 27 32 27 3 15 SSI AC97 Comm...

Page 24: ...ay Alarm Register RTC_ALRM_DAY 28 9 28 3 11 RTC General Oscillator Clock Upper Register RTC_GOCU 28 10 28 3 12 RTC General Oscillator Clock Lower Register RTC_GOCL 28 10 28 4 Functional Description 28 11 28 4 1 Clock Generation and Counter 28 11 28 4 2 Alarm 28 12 28 4 3 Sampling Timer 28 12 28 4 4 Minute Stopwatch 28 13 28 5 Initialization Application Information 28 13 28 5 1 Flow Chart of RTC Op...

Page 25: ... 3 4 Output Mode 30 9 30 4 Initialization Application Information 30 9 30 4 1 Code Example 30 9 30 4 2 Calculating Time Out Values 30 10 Chapter 31 DMA Serial Peripheral Interface DSPI 31 1 Introduction 31 1 31 1 1 Block Diagram 31 1 31 1 2 Overview 31 1 31 1 3 Features 31 2 31 1 4 Modes of Operation 31 3 31 2 External Signal Description 31 4 31 2 1 Signal Overview 31 4 31 2 2 Peripheral Chip Sele...

Page 26: ...ation Application Information 31 38 31 5 1 How to Change Queues 31 38 31 5 2 Switching Master and Slave Mode 31 38 31 5 3 Baud Rate Settings 31 38 31 5 4 Delay Settings 31 39 31 5 5 Calculation of FIFO Pointer Addresses 31 40 Chapter 32 UART Modules 32 1 Introduction 32 1 32 1 1 Overview 32 1 32 1 2 Features 32 2 32 2 External Signal Description 32 3 32 3 Memory Map Register Definition 32 3 32 3 1...

Page 27: ...2ADR 33 3 33 2 2 I2 C Frequency Divider Register I2FDR 33 3 33 2 3 I2 C Control Register I2CR 33 4 33 2 4 I2 C Status Register I2SR 33 5 33 2 5 I2 C Data I O Register I2DR 33 6 33 3 Functional Description 33 7 33 3 1 START Signal 33 7 33 3 2 Slave Address Transmission 33 8 33 3 3 Data Transfer 33 8 33 3 4 Acknowledge 33 9 33 3 5 STOP Signal 33 9 33 3 6 Repeated START 33 9 33 3 7 Clock Synchronizat...

Page 28: ...11 Extended Trigger Definition Register XTDR 34 22 34 4 Functional Description 34 26 34 4 1 Background Debug Mode BDM 34 26 34 4 2 Real Time Debug Support 34 49 34 4 3 Concurrent BDM and Processor Operation 34 52 34 4 4 Real Time Trace Support 34 52 34 4 5 Processor Status Debug Data Definition 34 57 34 4 6 Freescale Recommended BDM Pinout 34 63 Chapter 35 IEEE 1149 1 Test Access Port JTAG 35 1 In...

Page 29: ... 4 2 TAP Controller 35 6 35 4 3 JTAG Instructions 35 7 35 5 Initialization Application Information 35 10 35 5 1 Restrictions 35 10 35 5 2 Nonscan Chain Operation 35 10 Appendix A Revision History A 1 Changes Between Rev 2 and Rev 3 1 1 A 2 Changes Between Rev 3 and Rev 4 1 3 A 3 Changes Between Rev 4 and Rev 5 1 5 A 4 Changes Between Rev 5 and Rev 6 1 5 ...

Page 30: ...lity for infringement of any proprietary rights relating to use of information in the EHCI specification Intel may make changes to the EHCI specifications at any time without notice Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products with this ColdFire processor It is assumed that the reader understands operating sy...

Page 31: ...p www freescale com coldfire Conventions This document uses the following notational conventions cleared set When a bit takes the value zero it is said to be cleared when it takes a value of one it is said to be set MNEMONICS In text instruction mnemonics are shown in uppercase mnemonics In code and tables instruction mnemonics are shown in lowercase italics Italics indicate variable command param...

Page 32: ... register fields are used R 0 Indicates a reserved bit field in a memory mapped register These bits are always read as zeros W R 1 Indicates a reserved bit field in a memory mapped register These bits are always read as ones W R FIELDNAME Indicates a read write bit W R FIELDNAME Indicates a read only bit field in a memory mapped register W R Indicates a write only bit field in a memory mapped regi...

Page 33: ...xxviii Freescale Semiconductor ...

Page 34: ...als include a PCI bus controller ATA controller Fast Ethernet controllers and an encryption coprocessor 1 1 MCF5445x Family Comparison The following table compares the various device derivatives available within the MCF5445x family Table 1 1 MCF5445x Family Configurations Module MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455 ColdFire Version 4 Core with EMAC Enhanced Multiply Accumulate Uni...

Page 35: ...chdog Timer WDT Periodic Interrupt Timers PIT 4 4 4 4 4 4 Edge Port Module EPORT Interrupt Controllers INTC 2 2 2 2 2 2 16 channel Direct Memory Access DMA General Purpose I O GPIO JTAG IEEE 1149 1 Test Access Port Package 256 MAPBGA 360 TEPBGA Table 1 1 MCF5445x Family Configurations continued Module MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455 ...

Page 36: ...Edge port module FEC Fast Ethernet controller GPIO General Purpose Input Output I2 C Inter Intergrated Circuit INTC Interrupt controller JTAG Joint Test Action Group interface MMU Memory management unit PCI Peripheral Component Interconnect PIT Programmable interrupt timers PLL Phase locked loop module RNG Random Number Generator RTC Real time clock SSI Synchronous Serial Interface USB OTG Univers...

Page 37: ...PROM and FRAM devices Crossbar switch technology XBS for concurrent access to peripherals or RAM from multiple bus masters 16 channel DMA controller 16 bit 133MHz DDR mobile DDR DDR2 Controller USB 2 0 On the Go controller with ULPI support 32 bit PCI controller at 66 MHz ATA ATAPI controller 2 10 100 Ethernet MACs Coprocessor for acceleration of the DES 3DES AES MD5 and SHA 1 algorithms Random nu...

Page 38: ... bus masters e g FEC DMA USB OTG and PCI controllers via the crossbar switch Non blocking independent 16 Kbyte data and instruction caches organized as 4 way set associative with 16 bytes per cache line and 1024 cache lines supporting copy back and write through modes of operation 1 6 3 Phase Locked Loop PLL 16 40 MHz reference crystal Loss of lock detection 1 6 4 Power Management Fully static ope...

Page 39: ...I Bus Compatible with PCI 2 2 specification Supports up to 4 external PCI masters 32 bit target and intiator operation 33 66 MHz operation with PCI bus to internal bus divider ratios of 1 1 1 2 1 3 2 3 and 1 4 1 6 10 Universal Serial Bus USB 2 0 On The Go OTG Controller Support for full speed FS and low speed LS via a serial interface or on chip FS LS transceiver Optional UTMI Low Pin Count Interf...

Page 40: ...Synchronous Serial Interface SSI Supports shared synchronous transmit and receive sections Normal mode operation using frame sync Network mode operation allowing multiple devices to share the port with as many as 32 time slots Gated clock mode operation requiring no frame sync Programmable data interface modes such as I2 S LSB aligned and MSB aligned Programmable word length up to 24 bits AC97 sup...

Page 41: ...ration determined by reference input oscillator clock frequency and value programmed into user accessible registers Ability to wake the processor from low power modes wait doze and stop via the RTC interrupts 1 6 18 Software Watchdog Timer 16 bit down counter which resets the device if not serviced 1 6 19 Programmable Interrupt Timers PIT Four programmable interrupt timers each with a 16 bit count...

Page 42: ...ector number for each interrupt source Ability to mask any individual interrupt source plus a global mask all capability Support for service routine software interrupt acknowledge IACK cycles Combinational path to provide wake up from low power modes 1 6 25 Edge Port Module Each pin can be individually configured as low level sensistive interrupt pin or edge detecting interrupt pin rising falling ...

Page 43: ... optional data 1 6 29 JTAG Support JTAG part identification and part revision numbers 1 7 Memory Map Overview Table 1 2 illustrates the overall memory map of the device Table 1 2 System Memory Map Internal Address 31 28 Address Range Destination Slave Slave Memory Size 00xx 0x0000_0000 0x3FFF_FFFF FlexBus 1024 MB 01xx 0x4000_0000 0x7FFF_FFFF SDRAM Controller 1024 MB 1000 0x8000_0000 0x8FFF_FFFF In...

Page 44: ...Space The internal peripheral space contains locations for all internal registers used to program and control the device s functional blocks and external interfaces Table 1 3 summarizes the various register spaces and their base addresses Each slot is 16 kB in size which is not necessarily taken up entirely by the functional blocks Any slot not illustrated is reserved See corresponding chapter for...

Page 45: ...MA Timer 2 0xFC07_C000 31 DMA Timer 3 0xFC08_0000 32 PIT 0 0xFC08_4000 33 PIT 1 0xFC08_8000 34 PIT 2 0xFC08_C000 35 PIT 3 0xFC09_4000 37 Edge Port 0xFC0A_0000 40 CCM Reset Controller Power Management 0xFC0A_4000 41 Pin Multiplexing and Control GPIO 0xFC0A_8000 42 PCI Controller 0xFC0A_C000 43 PCI Arbiter 0xFC0B_0000 44 USB On the Go 0xFC0B_4000 45 RNG 0xFC0B_8000 46 SDRAM Controller 0xFC0B_C000 47...

Page 46: ... indicated with an overbar 2 2 Signal Properties Summary The below table lists the signals grouped by functionality NOTE In this table and throughout this document a single signal within a group is designated without square brackets i e FB_AD23 while designations for multiple signals within a group use brackets i e FB_AD 23 21 and is meant to include all signals within the two bracketed numbers wh...

Page 47: ...TOUT O EVDD M15 B17 Clock EXTAL PCI_CLK I EVDD M16 A16 XTAL U3 O EVDD L16 A17 Mode Selection BOOTMOD 1 0 I EVDD M5 M7 AB17 AB21 FlexBus FB_AD 31 24 PFBADH 7 0 4 FB_D 31 24 I O EVDD A14 A13 D12 C12 B12 A12 D11 C11 J2 K4 J1 K1 3 L1 L4 FB_AD 23 16 PFBADMH 7 0 4 FB_D 23 16 I O EVDD B11 A11 D10 C10 B10 A10 D9 C9 L2 L3 M1 4 N1 2 FB_AD 15 8 PFBADML 7 0 4 FB_D 15 8 I O EVDD B9 A9 D8 C8 B8 A8 D7 C7 P1 2 R1...

Page 48: ... 15 G15 13 F14 13 E15 13 D16 B16 C15 B15 C14 D15 C16 D14 PCI_CBE 3 0 I O EVDD G4 E4 D1 B1 PCI_DEVSEL O EVDD F2 PCI_FRAME I O EVDD B2 PCI_GNT3 PPCI7 ATA_DMACK O EVDD B7 PCI_GNT 2 1 PPCI 6 5 O EVDD C8 C9 PCI_GNT0 PCI_EXTREQ PPCI4 O EVDD A9 PCI_IDSEL I EVDD D5 PCI_IRDY I O EVDD C3 PCI_PAR I O EVDD C4 PCI_PERR I O EVDD B4 PCI_REQ3 PPCI3 ATA_INTRQ I EVDD C7 PCI_REQ 2 1 PPCI 2 1 I EVDD D7 C5 PCI_REQ0 PC...

Page 49: ...0 T11 R11 P11 L21 K22 K21 K20 J20 J19 J21 J22 H20 G22 G21 G20 G19 F22 F21 F20 SD_DM 3 2 O SDVDD P9 N12 H21 E21 SD_DQS 3 2 O SDVDD R9 N11 H22 E22 SD_RAS O SDVDD P5 N21 SD_VREF I SDVDD M8 M21 SD_WE O SDVDD R5 N20 External Interrupts Port6 IRQ7 PIRQ7 I EVDD L1 ABB13 IRQ4 PIRQ4 SSI_CLKIN I EVDD L2 ABB13 IRQ3 PIRQ3 I EVDD L3 AB14 IRQ1 PIRQ1 PCI_INTA I EVDD F15 C6 FEC0 FEC0_MDC PFECI2C3 O EVDD F3 AB8 FE...

Page 50: ...D K1 W11 FEC0_TXER PFEC0L4 ULPI_DATA0 O EVDD K2 AB12 FEC1 FEC1_MDC PFECI2C5 ATA_DIOR O EVDD W20 FEC1_MDIO PFECI2C4 ATA_DIOW I O EVDD Y22 FEC1_COL PFEC1H4 ATA_DATA7 I EVDD AB18 FEC1_CRS PFEC1H0 ATA_DATA6 I EVDD AA18 FEC1_RXCLK PFEC1H3 ATA_DATA5 I EVDD W14 FEC1_RXDV PFEC1H2 FEC1_RMII_ CRS_DV ATA_DATA15 I EVDD AB15 FEC1_RXD 3 2 PFEC1L 3 2 ATA_DATA 4 3 I EVDD AA15 Y15 FEC1_RXD1 PFEC1L1 FEC1_RMII_RXD1 ...

Page 51: ...0 PATAH 4 3 O EVDD W21 W22 ATA_DA 2 0 PATAH 2 0 O EVDD V19 21 ATA_RESET PATAL2 O EVDD W13 ATA_DMARQ PATAL1 I EVDD AA14 ATA_IORDY PATAL0 I EVDD Y14 Real Time Clock EXTAL32K I EVDD J16 A13 XTAL32K O EVDD H16 A12 SSI SSI_MCLK PSSI4 O EVDD T13 D20 SSI_BCLK PSSI3 U1CTS I O EVDD R13 E19 SSI_FS PSSI2 U1RTS I O EVDD P12 E20 SSI_RXD PSSI1 U1RXD UD I EVDD T12 D21 SSI_TXD PSSI0 U1TXD UD O EVDD R12 D22 I2C I2...

Page 52: ...N13 C20 UARTs U1CTS PUART7 I EVDD V3 U1RTS PUART6 O EVDD U4 U1RXD PUART5 I EVDD P3 U1TXD PUART4 O EVDD N3 U0CTS PUART3 I EVDD M3 Y16 U0RTS PUART2 O EVDD M2 AA16 U0RXD PUART1 I EVDD N1 AB16 U0TXD PUART0 O EVDD M1 W15 Note The UART1 and UART 2 signals are multiplexed on the DMA timers and I2C pins DMA Timers DT3IN PTIMER3 DT3OUT U2RXD I EVDD C13 H2 DT2IN PTIMER2 DT2OUT U2TXD I EVDD D13 H1 DT1IN PTIM...

Page 53: ...16 J7 J16 L7 L16 N16 P7 R16 T8 T12 T14 T16 SD_VDD L7 11 M9 M10 F19 H19 K19 M19 R19 U19 VDD_OSC L14 B16 VDD_A_PLL K15 C14 VDD_RTC M12 C13 VSS A1 A16 F6 11 G6 11 H6 11 J6 11 K6 11 T1 T16 A1 A22 B14 G7 G9 10 G12 13 G15 H7 H16 J9 14 K7 K9 14 K16 L9 14 M7 M9 M14 M16 N9 14 P9 14 P16 R7 T7 T9 11 T13 T15 AB1 AB22 VSS_OSC L15 C16 1 Pull ups are generally only enabled on pins with their primary function exc...

Page 54: ...ionality is determined by the edge port module The pin multiplexing and control module is only responsible for assigning the alternate functions 7 Depends on programmed polarity of the USB_VBUS_OC signal 8 Pull up when the serial boot facility SBF controls the pin 9 If JTAG_EN is asserted these pins default to Alternate 1 JTAG functionality The pin multiplexing and control module is not responsibl...

Page 55: ...rcuit is used to drive the crystal O RTC External Clock In EXTAL32K Crystal input clock for the real time clock module I RTC Crystal XTAL32K Oscillator output to EXTAL RTC crystal O FlexBus Clock Out FB_CLK Reflects one half of the internal bus clock or one fourth the core system clock fsys 4 O USB Clock In USB_CLKIN This pin allows the user to drive the reference clock to the USB module as an alt...

Page 56: ... or cache O Output Enable FB_OE Indicates when an external device can drive data during external read cycles O Transfer Acknowledge FB_TA Indicates external data transfer is complete During a read cycle when the processor recognizes TA it latches the data and then terminates the bus cycle During a write cycle when the processor recognizes TA the bus cycle is terminated I Read Write FB_R W Indicate...

Page 57: ...ates when valid data is on data bus I O SDRAM Write Data Byte Mask SD_DQM 3 2 Used to determine which byte lanes of data bus should be latched during a write cycle The SD_DQMn should be connected to individual SDRAM DQM signals Most SDRAMs associate DQM3 with the MSB in which case SD_DQM3 should be connected to the SDRAM s DQM3 input O SDRAM Column Address Strobe SD_CAS SDRAM column address strobe...

Page 58: ...ocessor needs to initiate a PCI transaction O PCI Initialization Device Select PCI_IDSEL Asserted during a PCI type 0 configuration cycle to address the PCI configuration header O PCI Initiator Ready PCI_IRDY Indicates that PCI initiator is ready to transfer data During a write operation assertion indicates the master is driving valid data on bus During a read operation assertion indicates that ma...

Page 59: ...eviation Function I O DMA Request DREQ 1 0 Asserted by an external device to request a DMA transfer I DMA Acknowledge DACK 1 0 Asserted by processor to indicate DMA request has been recognized O Table 2 12 Ethernet Module FEC Signals Signal Name Abbreviation Function I O Management Data FECn_MDIO Transfers control information between external PHY and the media access controller Data is synchronous...

Page 60: ...the FECn_RXDV input indicates that the PHY has valid nibbles present on the MII FECn_RXDV should remain asserted from the first recovered nibble of the frame through to the last Assertion of FECn_RXDV must start no later than the SFD and exclude any EOF I Receive Data 0 FECn_RXD0 FECn_RXD0 is the Ethernet input data transferred from the PHY to the media access controller when FECn_RXDV is asserted...

Page 61: ...word DMA or ultra DMA mode I ATA DMA Acknowledge ATA_DMACK This output signal is the ATA bus host DMA acknowledge It is asserted by the host when it grants the DMA request O ATA I O Ready In ATA_IORDY This input is the ATA IORDY line It has three functions IORDY active low wait during PIO cycles DDMARDY active low device ready during ultra DMA out transfers DSTROBE device strobe during ultra DMA i...

Page 62: ...timing for the decoding of the DSPI_PCS 3 0 signals which prevents glitches from occurring In slave mode this signal is not used O DSPI Peripheral Chip Selects DSPI_PCS 3 1 Provide DSPI peripheral chip selects that can be programmed to be active high or low O DSPI Peripheral Chip Select 0 Slave Select DSPI_PCS0 DSPI_SS In master mode DSPI_PCS0 is a peripheral chip select output that selects which ...

Page 63: ...nces based on whether USB is transmitting or receiving O ULPI Data Bus ULPI_DATA 7 0 These bi directional signals are ULPI data bus Synchronous to USB_CLKIN I O ULPI Next Data ULPI_NXT This input is the ULPI next data Synchronous to USB_CLKIN I ULPI Stop Data ULPI_STP This output is the ULPI stop data Synchronous to USB_CLKIN O ULPI Data Bus Direction ULPI_DIR This input is the ULPI data bus direc...

Page 64: ... logic I Test Mode Select TMS Used to sequence the JTAG state machine TMS is sampled on the rising edge of TCLK I Test Data Input TDI Serial input for test instructions and data TDI is sampled on the rising edge of TCLK I Test Data Output TDO Serial output for test instructions and data TDO is three stateable and actively driven in the shift IR and shift DR controller states TDO changes on the fal...

Page 65: ...n execution of RTE instruction 1000 Begin one byte transfer on PSTDDATA 1001 Begin two byte transfer on PSTDDATA 1010 Begin three byte transfer on PSTDDATA 1011 Begin four byte transfer on PSTDDATA 1100 Exception processing 1101 Reserved 1110 Processor is stopped 1111 Processor is halted Table 2 22 Test Signals Signal Name Abbreviation Function I O Test TEST Reserved for factory testing only and i...

Page 66: ...alog Supply VDD_A_PLL Dedicated power supply signal to isolate the sensitive PLL analog VCO circuitry from the normal levels of noise present on the digital power supply Oscillator VDD_OSC VSS_OSC Dedicated power supply signals to isolate the sensitive oscillator circuitry from the normal levels of noise present on the digital power supply Positive I O Supply EVDD These pins supply positive power ...

Page 67: ...Freescale Semiconductor 1 ...

Page 68: ...ldFire Family Programmer s Reference Manual The V4 ColdFire core includes the enhanced multiply accumulate unit EMAC and memory management unit MMU which are explained in detail in their own chapters This chapter also includes a full description of exception handling data formats an instruction set summary and a table of instruction timings 3 1 1 Overview As with all ColdFire cores the V4 ColdFire...

Page 69: ...rands and then executes the required function Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions Internal IAG IC1 IC2 IED IB DS OAG OC1 OC2 EX DA Branch Cache Branch Accel PSTDDATA DSO DSCLK DSI DDATA Debug Instruc...

Page 70: ...eline If the buffer is not empty the IFP stores the contents of the fetched instruction and its early decode information in the IB until it is required by the OEP The five stage operand execution pipeline structure is a key factor in the performance of the Version 4 ColdFire design The pipeline structure is termed a limited superscalar design because there are certain heavily used instruction cons...

Page 71: ... an arithmetic logic unit ALU The compute engine at the top of the OEP the address ALU is used typically for operand address calculations the execution ALU at the bottom is used for instruction execution The resulting structure provides almost 4 GB s read operand bandwidth at 250 MHz to the two compute engines and supports single cycle execution speeds for most instructions including all load and ...

Page 72: ...pervisor programming model that consists of registers available in user mode as well as the following control registers 16 bit status register SR 32 bit supervisor stack pointer SSP 32 bit vector base register VBR 32 bit cache control register CACR 32 bit access control registers ACR0 ACR1 ACR3 32 bit address space ID register ASID 32 bit MMU base address register MMUBAR Table 3 1 ColdFire Core Pr...

Page 73: ...W Contents of location 0x0000_0004 No 3 2 5 3 10 Supervisor Access Only Registers 0x002 Cache Control Register CACR 32 R W 0x0000_0000 Yes 3 2 6 3 10 0x003 Address Space Identifier ASID 8 R W 0x00 Yes 4 2 1 4 4 0x004 7 Access Control Register 0 3 ACR0 3 32 R W See Section Yes 6 3 2 6 8 0x008 MMU Base Address Register MMUBAR 32 R W 0x0000_0000 Yes 4 2 2 4 4 0x800 User Supervisor A7 Stack Pointer OT...

Page 74: ... and writes to the active A7 and OTHER_A7 It is the responsibility of the external development system to determine based on the setting of SR S the mapping of A7 and OTHER_A7 to the two program visible definitions SSP and USP This functionality is enabled by setting the enable user stack pointer bit CACR EUSP If this bit is cleared only a single stack pointer A7 originally defined for ColdFire ISA...

Page 75: ...ust be explicitly loaded after reset and before any compare CMP Bcc or Scc instructions are executed BDM Load 0x08F A7 Store 0x18F A7 0x800 OTHER_A7 Access A7 User or BDM read write OTHER_A7 Supervisor or BDM read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Address W Reset Figure 3 4 Stack Pointer Registers A7 and OTHER_A7 BDM LSB of Status Registe...

Page 76: ...ntains the base address of the exception vector table in the memory To access the vector table the displacement of an exception vector is added to the value in VBR The lower 20 bits of the VBR are not implemented by ColdFire processors They are assumed to be zero forcing the table to be aligned on a 1 MB boundary 2 Z Zero condition code bit Set if result equals zero otherwise cleared 1 V Overflow ...

Page 77: ...read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Base Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3 7 Vector Base Register VBR BDM 0x80E SR Access Supervisor read write BDM read write System Byte Condition Code Register CCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R T 0...

Page 78: ... associated with each pipeline stage are clearly visible 10 8 I Interrupt level mask Defines current interrupt level Interrupt requests are inhibited for all priority levels less than or equal to current level except edge sensitive level 7 requests which cannot be masked 7 0 CCR Refer to Section 3 2 4 Condition Code Register CCR Table 3 3 SR Field Descriptions continued Field Description 3 2 10 Me...

Page 79: ...3 Freescale Semiconductor Figure 3 9 Version 4 ColdFire Processor Operand Execution Pipeline Diagram OAG OC1 OC2 EX DS Index Base Register File EMAC BSU DIV Operand Memory Opword Extension 1 Extension 2 Extended Opword ...

Page 80: ...port for position independent code 3 Miscellaneous instruction additions to address new functionality Table 3 4 summarizes the instructions added to revision ISA_A to form revision ISA_C For more details see the ColdFire Family Programmer s Reference Manual Table 3 4 Instruction Enhancements over Revision ISA_A Instruction Description BITREV The contents of the destination data register are bit re...

Page 81: ... system stack pointed to by the supervisor stack pointer SSP As shown in Figure 3 10 the processor uses a simplified fixed length stack frame for all exceptions with additional fault status FS encodings to support the MMU The exception type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction fault or the address of the next in...

Page 82: ...ram counter 2 0x008 Fault Access error 3 0x00C Fault Address error 4 0x010 Fault Illegal instruction 5 0x014 Fault Divide by zero 6 7 0x018 0x01C Reserved 8 0x020 Fault Privilege violation 9 0x024 Next Trace 10 0x028 Fault Unimplemented line A opcode 11 0x02C Fault Unimplemented line F opcode 12 0x030 Next Non PC breakpoint debug interrupt 13 0x034 Next PC breakpoint debug interrupt 14 0x038 Fault...

Page 83: ...ld FS 3 0 at the top of the system stack This field is defined for access and address errors only and written as zeros for all other exceptions See Table 3 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSP Format FS 3 2 Vector FS 1 0 Status Register 0x4 Program Counter Figure 3 10 Exception Stack Frame Form Table 3 6 Format Field Encodings Original SSP Tim...

Page 84: ...nstruction restart from this class of exceptions See Section 3 3 4 16 Precise Faults for additional information If the MMU is disabled access errors are reported only with an attempted store to write protected memory Therefore access errors associated with instruction fetch or operand read accesses are not possible The Version 4 ColdFire processor unlike the Version 2 and 3 ColdFire processors upd...

Page 85: ...sizes 16 32 or 48 bits The first instruction word is known as the operation word or opword while the optional words are known as extension word 1 and extension word 2 The opword is further subdivided into three sections the upper four bits segment the entire ISA into 16 instruction lines the next 6 bits define the operation mode opmode and the low order 6 bits define the effective address See Figu...

Page 86: ...on Normally this opcode is a supervisor mode instruction but if the debug module s CSR UHE is set then this instruction can be also be executed in user mode for debugging purposes 3 3 4 6 Trace Exception To aid in program development all ColdFire processors provide an instruction by instruction tracing capability While in trace mode indicated by setting of the SR T bit the completion of an instruc...

Page 87: ...e exceptions which are generated in response to hardware breakpoint register triggers The processor does not generate an IACK cycle but rather calculates the vector number internally vector number 12 or 13 depending on the type of breakpoint trigger Additionally SR M I are unaffected by the interrupt Separate exception vectors are provided for PC breakpoints and for address data breakpoints In the...

Page 88: ...lt Halt If a ColdFire processor encounters any type of fault during the exception processing of another fault the processor immediately halts execution with the catastrophic fault on fault condition A reset is required to to exit this state 3 3 4 15 Reset Exception Asserting the reset input signal RESET to the processor causes a reset exception The reset exception has the highest priority of any e...

Page 89: ...re Configuration Info Table 3 9 D0 Hardware Configuration Info Field Description Field Description 31 24 PF Processor family This field is fixed to a hex value of 0xCF indicating a ColdFire core is present 23 20 VER ColdFire core version number Defines the hardware microarchitecture version of ColdFire core 0001 V1 ColdFire core 0010 V2 ColdFire core 0011 V3 ColdFire core 0100 V4 ColdFire core Thi...

Page 90: ...ue used for this device 1000 ISA_A Else Reserved 3 0 DEBUG Debug module revision number Defines revision level of the debug module used in the ColdFire processor core 0000 DEBUG_A 0001 DEBUG_B 0010 DEBUG_C 0011 DEBUG_D 0100 DEBUG_E 1001 DEBUG_B 1011 DEBUG_D This is the value used for this device 1111 DEBUG_D PST Buffer Else Reserved BDM Load 0x081 D1 Store 0x181 D1 Access User read only BDM read o...

Page 91: ...nstruction cache Else Reserved 23 16 Reserved 15 14 MBSZ Bus size Defines the width of the ColdFire master bus datapath 00 32 bit system bus datapath This is the value used for this device 01 64 bit system bus datapath Else Reserved 13 CPES CPUSHL enhancements supported Specifies whether the enhancements to the CPUSHL instructions are supported by the processor core See Section 6 4 8 CPUSHL Enhanc...

Page 92: ...orts this concept for most instructions program visible registers are updated only in the final OEP stage when fault collection is complete If any exception occurs pending register updates are discarded For V4 ColdFire cores and later most single cycle instructions naturally support precise faults and instruction restart while complex instruction do not Consider the following memory to memory move...

Page 93: ...ccess can be tagged if an instruction fetch terminates with an error acknowledge IFP access errors are recognized after the buffered instruction enters the OEP NOTE For access errors signaled on instruction prefetches an access error exception is generated only if instruction execution is attempted If an instruction fetch access error exception is generated and the FS field indicates the fault occ...

Page 94: ...1 the move l instruction waits three cycles for the muls l to update D0 If consecutive instructions update a register and use that register as a base of index value with a scale factor of 1 Xi l 1 in an address calculation a 2 cycle pipeline stall occurs If the destination register is used as an index register with any other scale factor Xi l 2 Xi l 4 a 3 cycle stall occurs NOTE Address register r...

Page 95: ...xxx wl Dy 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 1 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 Ay 1 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 Ay 1 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 d16 Ay 1 1 0 2 1 1 2 1 1 2 1 1 2 1 1 d8 Ay Xi SF 2 1 0 3 1 1 3 1 1 3 1 1 xxx w 1 1 0 2 1 1 2 1 1 2 1 1 xxx l 1 1 0 2 1 1 2 1 1 2 1 1 d16 PC 1 1 0 2 1 1 2 1 1 2 1 1 2 1 ...

Page 96: ...YTEREV Dx 1 0 0 CLR B ea 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 CLR W ea 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 CLR L ea 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 EXT W Dx 1 0 0 EXT L Dx 1 0 0 EXTB L Dx 1 0 0 FF1 Dx 1 0 0 NEG L Dx 1 0 0 NEGX L Dx 1 0 0 NOT L Dx 1 0 0 SATS L Dx 1 0 0 SCC Dx 1 0 0 SWAP Dx 1 0 0 TAS B ea 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 TST B ea 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0...

Page 97: ... BCLR Dy ea 2 0 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 BCLR imm ea 2 0 0 2 1 1 2 1 1 2 1 1 2 1 1 BSET Dy ea 2 0 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 BSET imm ea 2 0 0 2 1 1 2 1 1 2 1 1 2 1 1 BTST Dy ea 2 0 0 1 1 0 1 1 0 1 1 0 1 1 0 2 1 0 1 1 0 BTST imm ea 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 CMP B ea Rx 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 2 1 0 1 1 0 1 0 0 CMP W ea Rx 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 2 1 0 1 1 0 ...

Page 98: ...Dy Dx 1 0 0 Table 3 17 Miscellaneous Instruction Execution Times Opcode EA Effective Address Rn An An An d16 An d8 An Xn SF xxx wl xxx CPUSHL Ax 9 0 1 CPUSHL bc Ax 18 0 1 CPUSHL dc Ax 12 0 1 CPUSHL ic Ax 18 0 1 INTOUCH Ay 19 1 0 LINK W Ay imm 2 0 1 MOV3Q L imm ea 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 MOVE L Ay USP 3 0 0 MOVE L USP Ax 3 0 0 MOVE W CCR Dx 1 0 0 MOVE W ea CCR 1 0 0 1 0 0 MOVE W S...

Page 99: ... the processor begins sampling continuously for interrupts 4 PEA execution times are the same for d16 PC 5 PEA execution times are the same for d8 PC Xn SF Table 3 18 EMAC Instruction Execution Times Opcode EA Effective Address Rn An An An d16 An d8 An Xn SF xxx wl xxx MAC L Ry Rx Raccx 1 0 0 MAC L Ry Rx ea Rw Raccx 1 1 0 1 1 0 1 1 0 1 1 0 1 MAC W Ry Rx Raccx 1 0 0 MAC W Ry Rx ea Rw Raccx 1 1 0 1 ...

Page 100: ...accext23 ea x 1 0 0 MSAC L Ry Rx Raccx 1 0 0 MSAC W Ry Rx Raccx 1 0 0 MSAC L Ry Rx ea Rw Raccx 1 1 0 1 1 0 1 1 0 1 1 0 1 MSAC W Ry Rx ea Rw Raccx 1 1 0 1 1 0 1 1 0 1 1 0 1 MULS L ea y Dx 4 0 0 4 1 0 4 1 0 4 1 0 4 1 0 MULS W ea y Dx 4 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 4 0 0 MULU L ea y Dx 4 0 0 4 1 0 4 1 0 4 1 0 4 1 0 MULU W ea y Dx 4 0 0 4 1 0 4 1 0 4 1 0 4 1 0 5 1 0 4 1 0 4 0 0 1 Effective ...

Page 101: ...g on the amount of decoupling between the IFP and OEP the resulting execution times can vary from 1 to 3 cycles For the remaining ea values for the JSR instruction the branch acceleration logic is not used and the execution times are fixed 3 For the RTS opcode the timing depends on the prediction results of the hardware return stack a If predicted correctly 2 1 0 b If mispredicted 9 1 0 c If not p...

Page 102: ...d control status and fault registers that provide access to translation lookaside buffers TLBs Software can control address translation and access attributes of a virtual address by configuring MMU control registers and loading TLBs With software support the MMU provides demand paged virtual addressing 4 1 1 Block Diagram Figure 4 1 shows the placement of the MMU TLB hardware It follows a traditio...

Page 103: ...apped control status and fault registers Supports a flexible software defined virtual environment Internal IAG IC1 IC2 IED IB DS OAG OC1 OC2 EX DA Branch Cache Branch Accel PSTDDATA DSO DSCLK DSI DDATA Debug Instruction Fetch Pipeline Operand Execution Pipeline Instruction Memory Data Misalignment Operand Memory Module PSTCLK secDS Bus Memory Management Unit MMU ...

Page 104: ...isor control register at 0x008 accessed using MOVEC or the serial BDM debug port The ColdFire Programmers Reference Manual describes the MOVEC instruction MMUBAR holds the base address for the 64 Kbyte MMU memory map Table 4 1 The MMU memory map area is not visible unless the MMUBAR is valid and must be referenced aligned A large map portion is reserved for future use Table 4 1 MMU Memory Map Addr...

Page 105: ... 0 R ID W Reset 0 0 0 0 0 0 0 0 Figure 4 2 Address Space ID ASID Table 4 2 ASID Field Descriptions Field Description 7 0 ID This 8 bit field is the current user ASID The ASID is an extension to the virtual address Address space 0x00 may be reserved for supervisor mode See address space mode functionality in Section 4 2 3 MMU Control Register MMUCR The other 255 address spaces are used to tag user ...

Page 106: ... 0 0 0 0 Figure 4 4 MMU Control Register MMUCR Table 4 4 MMUCR Field Descriptions Bits Description 31 2 Reserved must be cleared 1 ASM Address space mode Controls how the address space ID is used for TLB hits 0 TLB entry ASID values are compared to the ASID register value for user or supervisor mode unless the TLB entry is marked shared MMUTR SG 1 The address space ID register value is the effecti...

Page 107: ...its of locked entries do not update hardware replacement algorithm information This is so access error handlers mapped with locked TLB entries do not influence the replacement algorithm Further TLB search operations do not update the hardware replacement algorithm information TLB writes loads do update the hardware replacement algorithm information The algorithm that chooses the allocation address...

Page 108: ... on the ITLB instruction operation bit MMUBAR Offset 0x008 MMUSR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPF RF WF 0 HIT 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4 6 MMU Status Register MMUSR Table 4 6 MMUSR Field Descriptions Field Desc...

Page 109: ... Last data access fault or search TLB operation did not hit in the TLB 1 Last data access fault or search TLB operation hit in the TLB 0 Reserved must be cleared MMUBAR Offset 0x010 MMUAR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4 7 MMU Fault Test ...

Page 110: ... the ASID register value for user mode unless the TLB entry is marked shared SG 1 The TLB entry ASID value may be compared to 0x00 for supervisor accesses or to the ASID The description of MMUCR ASM in Table 4 4 gives details on supervisor mode and ASID compares 1 SG Shared global Indicates when the entry is shared among user address spaces If an entry is shared its ASID is not part of the TLB hit...

Page 111: ...ess error exception 4 R Read access enable Indicates if data read accesses to this entry are allowed If a Harvard TLB implementation is used this bit is a don t care for the ITLB This bit is ignored on writes and always reads as zero for the ITLB 0 Do not allow data read accesses Attempted data read accesses that match this entry generate an access error exception 1 Allow data read accesses 3 W Wr...

Page 112: ...logic internal memories and internal to external memory bus controller function as in previous ColdFire versions with the addition of MMU MMU its TLB and associated control reside in the processor local bus logic MMU appears as a memory mapped device in the processor local bus space Information for access error fault processing is stored in MMU A precise processor local bus fault transfer error ac...

Page 113: ...R memory spaces are treated as physical address spaces and all permissions applying to these spaces are contained in the respective mapping register The virtual mode access either hits or misses in the TLB of the MMU A TLB miss generates an access fault in the processor allowing software to either load the appropriate translation into the TLB and restart the faulting instruction or abort the proce...

Page 114: ...s 0x0_1000 loads cache set 0x00 using virtual address 0x0_1400 loads cache set 0x40 This puts two copies of the same physical address in the cache making this memory space not coherent To avoid this problem software must force low order virtual page number bits to be equal to low order physical address bits for all bits used to address the cache set 4 3 1 2 6 Supervisor User Stack Pointers To isol...

Page 115: ...Rx_Hit 1 else if address 31 24 and ACRn 23 16 ACRn 31 24 and ACRn 23 16 ACRx_Hit 1 Table 4 10 New ACR and CACR Bits Field Description ACRn 10 AMM Address mask mode Determines access to the associated address space 0 The ACR hit function is the same as previous versions allowing control of a 16 Mbyte or greater memory region 1 The upper 8 bits of the address and ACR are compared without a mask func...

Page 116: ...played as part of real time trace When enabled real time trace displays instruction addresses on any change of flow instruction that is not absolute or PC relative For debug revision D architecture the address display is expanded to include ASID contents optionally thus providing the complete instruction virtual address on these instructions Additionally when a SYNC_PC serial BDM command is loaded...

Page 117: ...nd a 4 bit fault status field FS The first longword contains the 16 bit format vector word F V and the 16 bit status register The second contains the 32 bit program counter address of the faulted instruction For more information see Section 3 3 3 1 Exception Stack Frame Definition The FS field is used for access and address errors To optimize TLB miss exception handling new FS encodings as shown i...

Page 118: ...No write protection Unless the CPU space IACK mask bit is set interrupt acknowledge cycles and emulator mode operations are allowed to hit in RAMBAR All other operations are normal mode accesses Normal mode accesses For these accesses an effective cache mode precision and write protection are calculated for each request For data a normal mode access address is compared with the following priority ...

Page 119: ...n TLBs Fault free virtual address accesses that hit in the TLB incur no pipeline delay Accesses that miss the TLB or hit the TLB but violate an access attribute generate an access error exception On an access error software can reference address and information registers in the MMU to retrieve data Depending on the fault source software can obtain and load a new TLB entry modify the attributes of ...

Page 120: ...ruction and data processor local bus request Figure 4 1 shows how the MMU and memory unit access controllers fit in the processor local bus pipeline As the diagram shows core address and attributes access the mapping registers and the MMU By the middle of the KC1 cycle the physical memory address is available along with its corresponding access control Figure 4 11 shows more details of the MMU str...

Page 121: ...0 have this address format The remaining TLB allocation address bits AA 15 6 are ignored on updates and always read as zero When the MMUAR register is used for a TLB address bits FA 5 0 also have this address format The remaining form address bits FA 31 6 are ignored when this register is used for a TLB address JADDR J Control TLB Hit entries Comp TLB tag entries TLB data entry TLB hit data KC1 J ...

Page 122: ...ies are valid use the entry indicated by the PLRU as the allocate entry The PLRU algorithm uses 31 most recently used state bits per TLB to track the TLB hit history Table 4 14 lists these state bits Table 4 14 PLRU State Bits State Bits Meaning rdRecent31To16 A 1 indicates 31To16 is more recent than 15To00 rdRecent31To24 A 1 indicates 31To24 is more recent than 23To16 rdRecent15To08 A 1 indicates...

Page 123: ...ion operands straddle two pages Therefore one instruction may take two ITLB misses and allocate two ITLB pages before completion Likewise one instruction may require four DTLB misses and allocate four DTLB pages Because of this a pool of unlocked TLB entries must be available if virtual memory is used The above examples show the fewest entries needed to guarantee an instruction can complete execut...

Page 124: ...Refer to the ColdFire Programmer s Reference Manual for more information KC1 J Current address space ID ASID Compare IC1 or OC1 translated address IC1 or OC1 access control TLB Tag Entry 31 TLB Tag Entry 0 TLB Tag Entry 31 TLB Tag Entry 0 To processor local bus control for instruction or DTLB miss logic Instruction or data hit select Instruction or data processor local bus address and attributes C...

Page 125: ...Freescale Semiconductor 1 ...

Page 126: ...le 32 bit accumulator The EMAC features a four stage pipeline optimized for 32 bit operands with a fully pipelined 32 32 multiply array and four 48 bit accumulators The first ColdFire MAC supported signed and unsigned integer operands and was optimized for 16x16 operations such as those found in applications including servo control and image compression As ColdFire based systems proliferated the d...

Page 127: ...timized for single cycle pipelined operations with a possible accumulation after product generation This functionality is common in many signal processing applications The ColdFire core architecture is also modified to allow an operand to be fetched in parallel with a multiply increasing overall performance for certain DSP operations Consider a typical filtering operation where the filter is defin...

Page 128: ...C Address Mask Register MASK 32 R W 0xFFFF_FFFF 5 2 2 5 6 0x806 MAC Accumulator 0 ACC0 32 R W Undefined 5 2 3 5 8 0x807 MAC Accumulator 0 1 Extension Bytes ACCext01 32 R W Undefined 5 2 4 5 8 0x808 MAC Accumulator 2 3 Extension Bytes ACCext23 32 R W Undefined 5 2 4 5 8 0x809 MAC Accumulator 1 ACC1 32 R W Undefined 5 2 3 5 8 0x80A MAC Accumulator 2 ACC2 32 R W Undefined 5 2 3 5 8 0x80B MAC Accumula...

Page 129: ... storing an accumulator to a general purpose register 0 Move accumulator without rounding to a 16 bit value Accumulator is moved to a general purpose register as a 32 bit value 1 The accumulator is rounded to a 16 bit value using the round to nearest even method when moved to a general purpose register See Section 5 3 1 1 Rounding The resulting 16 bit value is stored in the lower word of the desti...

Page 130: ...curs on a MAC or MSAC instruction indicating that the result cannot be represented in the limited width of the EMAC V is set only if a product overflow occurs or the accumulation overflows the 48 bit structure V is evaluated on each MAC or MSAC operation and uses the appropriate PAVn flag in the next state V evaluation 0 EV Extension overflow Signals that the last MAC or MSAC instruction overflowe...

Page 131: ...xFFFF MASK if ea An oa An An An 4 0xFFFF MASK if ea An oa An 4 0xFFFF MASK An An 4 0xFFFF MASK if ea d16 An oa An se_d16 0xFFFF0x MASK Here oa is the calculated operand address and se_d16 is a sign extended 16 bit displacement For auto addressing modes of post increment and pre decrement the updated An value calculation is also shown Use of the post increment addressing mode An with the MASK is su...

Page 132: ...r Extension Register ACCext01 BDM 0x806 ACC0 0x809 ACC1 0x80A ACC2 0x80B ACC3 Access User read write BDM read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Accumulator W Reset Table 5 5 ACC0 3 Field Descriptions Field Description 31 0 Accumulator Store 32 bits of the result of the MAC operation BDM 0x807 ACCext01 Access User read write BDM read write...

Page 133: ...s in these formats Signed integers Unsigned integers Signed fixed point fractional numbers The EMAC is optimized for single cycle pipelined 32 32 multiplications For word and longword sized integer input operands the low order 40 bits of the product are formed and used with the destination accumulator For fractional operands the entire 64 bit product is calculated and truncated or rounded to the m...

Page 134: ...ts and 32 bit ACCn contents the specific definitions are if MACSR 6 5 00 signed integer mode Complete Accumulator 47 0 ACCextn 15 0 ACCn 31 0 if MACSR 6 5 01 or 11 signed fractional mode Complete Accumulator 47 0 ACCextn 15 8 ACCn 31 0 ACCextn 7 0 if MACSR 6 5 10 unsigned integer mode Complete Accumulator 47 0 ACCextn 15 0 ACCn 31 0 The four accumulators are represented as an array ACCn where n se...

Page 135: ... efficiently move large data blocks by generating line sized burst references The ability to load an operand simultaneously from memory into a register and execute a MAC instruction makes some DSP operations such as filtering and convolution more manageable The programming model includes a mask register MASK which can optionally be used to generate an operand address during MAC MOVE instructions T...

Page 136: ... output datapath requires special care during the EMAC s save restore process In particular any result rounding modes must be disabled during the save restore process so the exact bit wise contents of the EMAC registers are accessed Consider the memory structure containing the EMAC programming model struct macState int acc0 int acc1 int acc2 int acc3 int accext01 int accext02 int mask int macsr ma...

Page 137: ... signed result Multiply Unsigned mulu ea y Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate mac Ry RxSF ACCx msac Ry RxSF ACCx Multiplies two operands and adds subtracts the product to from an accumulator Multiply Accumulate with Load mac Ry Rx ea y Rw ACCx msac Ry Rx ea y Rw ACCx Multiplies two operands and combines the product to an accumulator while loading a ...

Page 138: ...nsion bytes into a CPU register Store Accumulator Extensions 23 move l ACCext23 Rx Writes the contents of accumulator 2 3 extension bytes into a CPU register Table 5 8 EMAC Instruction Summary continued Command Mnemonic Description The EMAC execution pipeline overlaps the EX stage of the OEP the first stage of the EMAC pipeline is the last stage of the basic OEP EMAC units are designed for sustain...

Page 139: ... number that can be represented is 1 whose internal representation is 0x8000 and 0x8000_0000 respectively The largest positive word is 0x7FFF or 1 2 15 the most positive longword is 0x7FFF_FFFF or 1 2 31 Thus the number range for these signed fractional numbers is 1 0 1 0 5 3 5 MAC Opcodes MAC opcodes are described in the ColdFire Programmer s Reference Manual Remember the following Unless otherwi...

Page 140: ...ght shifts unless the product is zero For signed longword operations the sign bit is shifted into the product unless an overflow occurs or the product is zero in which case a zero is shifted in For all left shifts a zero is inserted into the lsb position The following pseudocode explains basic MAC or MSAC instruction functionality This example is presented as a case statement covering the three ba...

Page 141: ... case 3 SF 1 product 39 0 product 39 product 39 1 break if MACSR PAVn 0 then if inst MSAC then result 47 0 ACCx 47 0 product 47 0 else result 47 0 ACCx 47 0 product 47 0 check for accumulation overflow if accumulationOverflow 1 then MACSR PAVn 1 MACSR V 1 if MACSR OMC 1 then accumulation overflow saturationMode enabled if result 47 1 then result 47 0 0x0000_7fff_ffff else result 47 0 0xffff_8000_0...

Page 142: ...and combine with accumulator check for the 1 1 overflow case if operandY 31 0 0x8000_0000 operandX 31 0 0x8000_0000 then product 71 64 0x00 zero fill else product 71 64 8 product 63 sign extend if inst MSAC then result 47 0 ACCx 47 0 product 71 24 else result 47 0 ACCx 47 0 product 71 24 check for accumulation overflow if accumulationOverflow 1 then MACSR PAVn 1 MACSR V 1 if MACSR OMC 1 then accum...

Page 143: ...1 MACSR V 1 if inst MSAC MACSR OMC 1 then result 47 0 0x0000_0000_0000 else if MACSR OMC 1 then overflowed MAC saturationMode enabled result 47 0 0xffff_ffff_ffff zero fill to 48 bits before performing any scaling product 47 40 0 zero fill upper byte scale product before combining with accumulator switch SF 2 bit scale factor case 0 no scaling specified break case 1 SF 1 product 40 0 product 39 0 ...

Page 144: ...lt 47 0 0x0000_0000_0000 else if MACSR OMC 1 then overflowed MAC saturationMode enabled result 47 0 0xffff_ffff_ffff transfer the result to the accumulator ACCx 47 0 result 47 0 MACSR V MACSR PAVn MACSR N ACCx 47 if ACCx 47 0 0x0000_0000_0000 then MACSR Z 1 else MACSR Z 0 if ACCx 47 32 0x0000 then MACSR EV 0 else MACSR EV 1 break ...

Page 145: ...Enhanced Multiply Accumulate Unit EMAC 5 21 Freescale Semiconductor ...

Page 146: ... and four way set associative with a 16 byte line size The cache improves system performance by providing single cycle access to the instruction and data pipelines This decouples processor performance from system memory performance increasing bus availability for on chip DMA or external devices This device implements a special branch instruction cache for accelerating branches enabled by a bit in ...

Page 147: ...y misses the cache or if a write access must be written through to memory the cache performs a bus cycle on the internal bus and correspondingly on the external bus The cache module does not implement bus snooping cache coherency with other possible bus masters must be maintained in software 6 2 Cache Organization A four way set associative cache is organized as four ways levels There are 256 sets...

Page 148: ...ot contain the appropriate data for start up Because reset and power up do not invalidate cache lines automatically the cache should be cleared explicitly by setting CACR DCINVA ICINVA before the cache is enabled B After the entire cache is flushed cacheable entries are loaded first in way 0 If way 0 is occupied the cacheable entry is loaded into the same set in way 1 as shown in Figure 6 3 D This...

Page 149: ...Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Invalid V 0 Valid not modified V 1 M 0 Valid modified V 1 M 1 At reset cache contents are indeterminate V and M may be set The cache should be cleared explicitly by setting CACR DCINVA before the cache is enabled Setting CACR DCINVA invalidates the entire cache Set 0 Initial cacheable accesses to memory fill positions in way 0...

Page 150: ... Access Control Register 3 ACR3 32 R W Undefined Yes 6 3 2 6 8 1 The values listed in this column represent the Rc field used when accessing the core registers via the BDM port For more information see Chapter 34 Debug Module BDM 0x002 Access MOVEC write only Debug read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R DEC DW DESB DDPI DHLCK DDCM DC INVA DDSP 0 0 IVO BEC BC INVA 0 0 W Reset ...

Page 151: ...he RAMBARs or ACRs this field defines the effective cache mode 00 Cacheable write through imprecise 01 Cacheable copyback 10 Cache inhibited precise 11 Cache inhibited imprecise Precise and imprecise accesses are described in Section 6 4 1 2 Cache Inhibited Accesses 24 DCINVA Data cache invalidate all Setting this bit initiates entire cache invalidation After invalidation is complete this bit auto...

Page 152: ...0 Normal operation The cache allocates to the lowest invalid way if all ways are valid the cache allocates to the way pointed at by the round robin counter and then increments this counter 1 Half cache operation The cache allocates to the lowest invalid way of ways 2 and 3 if both of these ways are valid the cache allocates to way 2 if the high order bit of the round robin counter is zero otherwis...

Page 153: ...ss Compared with address bits A 31 24 Eligible addresses that match are assigned the access control attributes 23 16 ADMSK Address mask Setting a mask bit causes the corresponding address base bit to be ignored The low order mask bits can be set to define contiguous regions larger than 16 Mbytes The mask can define multiple non contiguous regions of memory 15 E Enable Enables or disables the other...

Page 154: ...Section 6 4 1 2 Cache Inhibited Accesses 00 Cacheable write through 01 Cacheable copyback 10 Cache inhibited precise 11 Cache inhibited imprecise 4 Reserved must be cleared 3 SP Supervisor protect 0 Indicates supervisor and user mode access allowed 1 Indicates only supervisor access is allowed to this address space and attempted user mode accesses generate an access error exception 2 W Write prote...

Page 155: ...e through the write is passed to system memory and the M bit is not used The tag does not have TT or TM bits To allocate a cache entry the cache set index selects one of the cache s 256 sets The cache control logic looks for an invalid cache line to use for the new entry If none are available the cache controller uses a pseudo round robin replacement algorithm to choose the line to be deallocated ...

Page 156: ... change the status bits and no deallocation or replacement occurs the data or instructions are read from the cache If the cache hits on a write access data is written to the appropriate portion of the accessed cache line Write hits in cacheable write through regions generate an external write cycle and the cache line is marked valid but is never marked modified Write hits in cacheable copyback reg...

Page 157: ... 3 reset does not automatically invalidate cache entries the software invalidates them The ACRs allow the defaults selected in the CACR to be overridden In addition some instructions for example CPUSHL and processor core operations perform accesses that have an implicit caching mode associated with them The following sections discuss the different caching accesses and their associated cache modes ...

Page 158: ...not cache the processor s memory mapped registers If the corresponding ACRn CM or CACR DDCM indicates cache inhibited precise or imprecise the access is cache inhibited The caching operation is identical for both cache inhibited modes which differ only regarding recovery from an external bus error In determining whether a memory location is cacheable or cache inhibited the CPU checks memory contro...

Page 159: ...es apply only when ACRn CM indicates precise mode and aligned accesses All CPU space register accesses such as MOVEC are treated as cache inhibited and precise 6 4 2 Cache Protocol The following sections describe the cache protocol for processor accesses and assumes that the data is cacheable that is write through or copyback The discussion of write operations applies to the data cache only 6 4 2 ...

Page 160: ...andles processor writes that hit in the data cache differently for write through and copyback regions For write hits to a write through region portions of cache lines corresponding to the size of the access are updated with the data The data is also written to external memory The cache line state is unchanged For copyback accesses the cache controller updates the cache line and sets the M bit for ...

Page 161: ... the burst read write enable bits CSCRn BSTR BSTW For more information regarding external bus burst mode accesses see Chapter 20 FlexBus The first cycle of a cache line read loads the longword entry corresponding to the requested address Subsequent transfers load the remaining longword entries A burst operation aborts by a write protection fault which is the only possible access error Exception pr...

Page 162: ...modes use the store buffer The store buffer can queue data as much as four bytes wide per entry Each entry matches the corresponding bus cycle it generates therefore a misaligned longword write to a write through region creates two entries if the address is to an odd word boundary It creates three entries if the address is to an odd byte boundary one per bus cycle 6 4 4 2 2 Push and Store Buffer B...

Page 163: ...y 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Invalid V 0 Valid not modified V 1 M 0 Valid modified V 1 M 1 After reset the cache is invalidated ways 0 and 1 are then written with data that should not be deallocated Ways 0 and 1 can be filled systematically by using the INTOUCH instruction After CACR DHLCK is set subsequent cache accesses go to ways 2 and 3 Set 0 While the cache is locked and after a po...

Page 164: ...A Disabling a cache by clearing CACR IEC or CACR DEC makes the cache non operational without affecting tags state information or contents The contents of Ax used with CPUSHL specify cache row and line indexes This differs from the MC68040 family where a physical address is specified Figure 6 9 shows the Ax format for the data and instruction cache The following code example flushes the entire data...

Page 165: ...reviously invalidated the default instruction cache mode is cacheable and the default operand cache mode is copyback This function must be mapped into a cache inhibited or SRAM space or these text lines are to be prefetched into the instruction cache This may displace some of the 8 Kbyte space being explicitly fetched instructionCacheLoadAndLock move l 0xa2088100 d0 enable and invalidate the instr...

Page 166: ...e 6 10 Instruction Cache Line State Diagram Table 6 5 describes the instruction cache state transitions shown in Figure 6 10 Table 6 5 Instruction Cache Line State Transitions Access Current State Invalid V 0 Valid V 1 Read miss II1 Read line from memory and update cache supply data to processor go to valid state IV1 Read new line from memory and update cache supply data to processor stay in valid...

Page 167: ...ry Figure 6 11 shows the three possible data cache line states and possible processor initiated transitions for memory configured as copyback Transitions are labeled with a capital letter indicating the previous state and a number indicating the specific case listed in Table 6 6 Figure 6 11 Data Cache Line State Diagram Copyback Mode Figure 6 12 shows the two possible states for a cache line in wr...

Page 168: ...tate Write miss write through WI3 Write data to memory stay in invalid state WV3 Write data to memory stay in valid state WD3 Write data to memory stay in modified state Cache mode changed for the region corresponding to this line To avoid this state execute a CPUSHL instruction or set CACR DCINVA ICINVA before switching modes Write hit copy back CI4 Not possible CV4 Write data to cache go to modi...

Page 169: ...I4 Not possible Write hit write through WI4 Not possible Cache invalidate C W I5 No action stay in invalid state Cache push C W I6 No action stay in invalid state Cache push C W I7 No action stay in invalid state Table 6 8 Data Cache Line State Transitions Current State Valid Access Response Read miss C W V1 Read new line from memory and update cache supply data to processor stay in valid state Re...

Page 170: ...tate Write miss copyback CD3 Push modified line to buffer read new line from memory and update cache write push buffer contents to memory stay in modified state Write miss write through WD3 Write data to memory stay in modified state Cache mode changed for the region corresponding to this line To avoid this state execute a CPUSHL instruction or set CACR DCINVA ICINVA before switching modes Write h...

Page 171: ... cache set address and way number for the baseline CPUSHL functionality or ax is the physical address for the enhanced CPUSHL For the enhanced implementations the specific operation performed by the CPUSHL instruction is defined by the state of four CACR bits See Table 6 10 Table 6 10 Enhanced CPUSHL Functionality Instruction CACR Bits Description 14 SPA 20 IVO 28 DDPI 12 IDPI Search by Action cpu...

Page 172: ...e ignore supervisor user cacheable writethrough movec D0 ACR0 cpushl ic ax 0 0 1 Cache address way No operation cpushl ic ax 0 1 Cache address way Invalidate inst cpushl ic ax 1 0 0 Physical address Clear instruction cpushl ic ax 1 0 1 Physical address No operation cpushl ic ax 1 1 Physical address Invalidate instruction cpushl nc ax Address intouch instruction Table 6 10 Enhanced CPUSHL Functiona...

Page 173: ...Cache 6 28 Freescale Semiconductor ...

Page 174: ...ated accesses or memory referencing commands from the debug module Depending on configuration information processor references may be sent to the cache and the SRAM block simultaneously If the reference maps into the region defined by the SRAM the SRAM provides the data back to the processor and the cache data is discarded Accesses from the SRAM module are not cached The SRAM is dual ported to pro...

Page 175: ... base address are 0x8000_0000 0x8FFF_8000 The address must be 0 modulo 32 K Set the RAMBAR register appropriately By default the RAMBAR is invalid but the backdoor is enabled In this state any core accesses to the SRAM are routed through the backdoor Therefore the SRAM is accessible by the core but it does not have a single cycle access time To ensure that the core has single cycle access to the S...

Page 176: ...mined according to the following table Note The recommended setting maximum performance for the priority bits is 00 9 BDE Backdoor Enable Allows access by non core bus masters via the SRAM backdoor on the crossbar switch 0 Non core crossbar switch master access to memory is disabled 1 Non core crossbar switch master access to memory is enabled 8 WP Write Protect Allows only read accesses to the SR...

Page 177: ...t describes how to initialize the SRAM The code sets the base address of the SRAM at 0x8000_0000 and initializes the SRAM to zeros RAMBASE EQU 0x80000000 set this variable to 0x80000000 RAMVALID EQU 0x00000001 5 1 C I SC SD UC UD Address Space Masks ASn These five bit fields allow types of accesses to be masked or inhibited from accessing the SRAM module The address space mask bits are C I CPU spa...

Page 178: ...nue looping 7 3 2 Power Management As noted previously depending on the RAMBAR defined configuration instruction fetch and operand read accesses may be sent to the SRAM and cache simultaneously If the access maps to the SRAM module it sources the read data and the cache access is discarded If the SRAM is used only for data operands setting the ASn bits associated with instruction fetches can decre...

Page 179: ...Static RAM SRAM 7 6 Freescale Semiconductor ...

Page 180: ...odule contains Crystal amplifier and oscillator OSC Phase locked loop PLL Status and control registers Control logic NOTE Throughout this manual fsys refers to the core frequency and fsys 2 refers to the internal bus frequency Figure 8 1 is a high level representation of clock connections The exact functionality of the blocks is not illustrated SBF controls many configuration options clocks to the...

Page 181: ...he SDRAMC SSI USB and real time clock contain some logic that uses the fsys 2 clock in addition to the module specific clock 7 When loading boot code via the SBF the device is clocked by the main oscillator fref V4 ColdFire Core Peripheral Bus Clock SRAM Cache FB_AD3 when 1 0 FlexBus PCI SDRAMC eDMA FECs PIT DMA Timers DSPI UART I2C GPIO BDM BOOTMOD 10 FB_AD4 when BOOTMODE 10 or MISCCR LIMP SSI AT...

Page 182: ...tion 8 2 1 PLL Control Register PCR for details The post VCO dividers can be enabled asynchronously or disabled via register Allows glitch free dynamic switching of the output divider Provides signals indicating when the PLL has acquired lock and lost lock 16 40 MHz reference crystal oscillator Support for low power modes Direct clocking of system by input clock bypassing the PLL Loss of lock rese...

Page 183: ... reset by overriding the default reset configuration See Chapter 11 Chip Configuration Module CCM for details on setting the device for external reference oscillator bypass mode 8 1 3 3 Input Clock Limp Mode Through parallel RCON serial boot or the MISCCR LIMP bit the device may be placed into a low frequency limp mode in which the PLL is bypassed and the device runs from a factor of the input clo...

Page 184: ...options for enabling or disabling the PLL or crystal oscillator in stop mode compromising between stop mode current and wake up recovery time The PLL can be disabled in stop mode but requires a wake up period before it relocks The oscillator can also be disabled during stop mode but it requires a wake up period to restart When the PLL is enabled in stop mode LPCR STPMD 00 the external FB_CLK signa...

Page 185: ... PCR 32 R W See Section 8 2 1 8 6 0xFC0C_4004 PLL Status Register PSR 32 R W 0x0000_0000 8 2 2 8 8 Address 0xFC0C_4000 PCR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PFDR 0 1 1 1 OUTDIV5 OUTDIV4 OUTDIV3 OUTDIV2 OUTDIV1 W Reset 360 TEPBGA See Note 0 1 1 1 0 1 1 1 See Note 0 1 1 1 0 0 1 1 0 0 0 1 Reset 256 MAPBGA See Note 0 1 1 1 0 ...

Page 186: ...tion A value of zero disables this clock Note The OUTDIV5 resulting frequency must be 60 MHz if used as the USB clock source Eqn 8 2 15 12 OUTDIV4 Output divider for generating the PCI clock frequency The divider is the value of this bit field plus 1 The reset value depends on the selected chip configuration See Chapter 11 Chip Configuration Module CCM for more information A value of zero disables...

Page 187: ...ld plus 1 The reset value depends on the selected chip configuration See Chapter 11 Chip Configuration Module CCM for more information A value of zero disables this clock Eqn 8 6 Note The maximum value restrictions on this field depend on the setting of OUTDIV2 and OUTDIV3 as shown below Address 0xFC0C_4004 PSR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1...

Page 188: ...ansition while the divider values are being synchronized Following the transition period all output clocks begin toggling at the new divider values simultaneously The transition from the old divider value to the new divider value takes no more than 100 ns Because the output divider transition takes a period of time to change the PCR may not be written back to back without waiting 100 ns between wr...

Page 189: ...signal does not indicate the PLL has locked to the input reference but the bypass clock is present on the output In bypass mode no PLL lock exists 8 3 3 Loss of Lock When the PLL loses lock the PSR LOCKS status bit is set If the PFDR is changed or if an unexpected loss of lock condition occurs the LOCKS status bit is set While the PLL is in an unlocked condition the system clocks continue to be so...

Page 190: ...PCI reference clock NOTE If PCI is enabled the input reference clock must be a bypass clock external oscillator and must also equal the PCI operating frequency The PCI controller can operate at frequencies other than what is shown in Table 8 5 but ensure that the input bypass clock frequency is the PCI operating frequency USB_CLKIN in the USB OTG column indicates that the USB On the Go module rece...

Page 191: ...gisters While in reset the PLL input clock is output to the device After RESET de asserts PLL output clocks generate however until the PSR LOCK bit is set the PLL output clock frequencies are not stable and within specification When this bit is set the PLL is in frequency lock 8 3 5 2 External Reset When RESET asserts the PLL input clock outputs to the device and the PLL does not begin acquiring l...

Page 192: ...Value Section Page Supervisor Access Only Registers1 1 User access to supervisor only address locations have no effect and result in a bus error 0xFC04_0013 Wakeup Control Register WCR 8 R W 0x00 9 2 1 9 2 0xFC04_002C Peripheral Power Management Set Register 0 PPMSR0 8 W 0x00 9 2 2 9 3 0xFC04_002D Peripheral Power Management Clear Register 0 PPMCR0 8 W 0x00 9 2 3 9 4 0xFC04_0030 Peripheral Power M...

Page 193: ...r mode control logic processes the entry into a low power mode and the appropriate clocks usually those related to the high speed processor core are disabled 4 After entering the low power mode the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests The device waits for an event to generate an interrupt request with a priority level greater than ...

Page 194: ...ble and writable in all modes 00 Run 01 Doze 10 Wait 11 Stop Note If WCR LPMD is cleared the device stops executing code upon a STOP instruction However no clocks disable 3 Reserved must be cleared 2 0 PRILVL Exit low power mode interrupt priority level This field defines the interrupt priority level to exit the low power mode Address 0xFC04_002C PPMSR0 Access Supervisor Write only 7 6 5 4 3 2 1 0...

Page 195: ...ss space that defines whether the module clock for the given space is enabled or disabled Because the operation of the crossbar switch and the system control module SCM are fundamental to the operation of the device the clocks for these modules cannot be disabled Table 9 3 PPMSR0 Field Descriptions Field Description 7 Reserved must be cleared 6 SAMCD Set all module clock disables 0 Set only those ...

Page 196: ...1 1 1 1 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CD47 CD46 CD45 CD44 CD43 CD42 CD41 CD40 1 1 CD37 1 CD35 CD34 CD33 CD32 W Reset 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 Figure 9 4 Peripheral Power Management High Register PPMHR0 Table 9 5 PPMHR0 CDn Assignments Slot Number CDn Peripheral 32 CD32 PIT 0 33 CD33 PIT 1 34 CD34 PIT 2 35 CD35 PIT 3 37 CD37 Edge Port 40 CD40 CCM Reset Controller Power Manage...

Page 197: ...5 Peripheral Power Management Low Registers PPMLR0 Table 9 6 PPMLR0 CDn Assignments Slot Number CDn Peripheral 2 CD2 FlexBus 12 CD12 FEC0 13 CD13 FEC1 15 CD15 Real Time Clock 17 CD17 eDMA Controller 18 CD18 Interrupt Controller 0 19 CD19 Interrupt Controller 1 21 CD21 IACK 22 CD22 I2 C 23 CD23 DSPI 24 CD24 UART0 25 CD25 UART1 26 CD26 UART2 28 CD28 DMA Timer 0 29 CD29 DMA Timer 1 30 CD30 DMA Timer ...

Page 198: ... bit must be written before execution of the STOP instruction for it to take effect 0 System clocks enabled only when PLL is locked or operating normally 1 System clocks enabled upon wake up from stop mode regardless of PLL lock status Note Setting this bit is potentially dangerous and unreliable The system may behave unpredictably when using an unlocked clock because the clock frequency could ove...

Page 199: ...minimum input clock frequency the SDRAM controller USB On to Go FECs PCI controller and ATA controller are not functional in limp mode 9 3 3 Low Power Modes The system enters a low power mode by executing a STOP instruction The low power mode the device actually enters stop wait or doze depends on the setting of the WCR LPMD bits Entry into any of these modes idles the CPU with no cycles active po...

Page 200: ...peration is properly terminated When exiting stop mode most peripherals retain their pre stop status and resume operation NOTE Entering stop mode disables the SDRAMC including the refresh counter If SDRAM is used code is required to ensure proper entry and exit from stop mode See Chapter 21 SDRAM Controller SDRAMC for more information 9 3 4 Peripheral Behavior in Low Power Modes The following subs...

Page 201: ...ip to reset and exit from any low power mode In wait and doze modes asserting the external RESET pin for at least four clocks causes an external reset that resets the chip and exits any low power modes In stop mode the RESET pin synchronization disables and asserting the external RESET pin asynchronously generates an internal reset and exit any low power modes Registers lose current values and mus...

Page 202: ... interrupts either an edge transition or low level on an external pin to exit the low power modes In stop mode no system clock is available to perform the edge detect function Therefore only the level detect logic is active if configured to allow any low level on the external interrupt pin to generate an interrupt if enabled to exit stop mode 9 3 4 10 eDMA Controller In wait and doze modes the eDM...

Page 203: ...xiting stop mode returns the FEC to operation from the state prior to stop mode entry 9 3 4 14 USB On the Go Module If the USB On the Go module is clocked externally it operates normally in wait and doze It is capable of generating an interrupt to wake up the core from the wait and doze modes In stop mode the USB module is disabled The USB block contains an automatic low power mode in which the mo...

Page 204: ...odule is unaffected and may generate an interrupt to exit these low power modes In stop mode the DSPI stops immediately and freezes operation register values state machines and external pins During this mode the DSPI clocks shut down Coming out of stop mode returns the DSPI to operation from the state prior to stop mode entry 9 3 4 21 UART Modules UART0 2 In wait and doze modes the UARTs are unaff...

Page 205: ...ty of an interrupt or reset by that peripheral to force the CPU into run mode Table 9 9 CPU and Peripherals in Low Power Modes Module Peripheral Status1 Wake up Procedure Wait Mode Doze Mode Stop Mode ColdFire Core Stopped N A Stopped N A Stopped N A SRAM Stopped N A Stopped N A Stopped N A Clock Module Enabled Interrupt Enabled Interrupt Program Interrupt Power Management Enabled N A Enabled N A ...

Page 206: ...rupt Stopped N A RNG Enabled Interrupt Enabled Interrupt Stopped N A JTAG2 Enabled N A Enabled N A Enabled N A BDM3 Enabled Yes Enabled Yes Enabled Yes 1 Program indicates that the peripheral function during the low power mode is dependent on programmable bits in the peripheral register map 2 The JTAG logic is clocked by a separate TCLK clock 3 Entering halt mode via the BDM port exits any lower p...

Page 207: ...Power Management 9 16 Freescale Semiconductor ...

Page 208: ...tures are based on the Enhanced Host Controller Interface Specification for Universal Serial Bus EHCI from Intel Corporation The USB OTG module can act as a host a device or an On The Go negotiable host device on the USB bus The USB 2 0 OTG module interfaces to the processor s ColdFire core The USB controller is programmable to support host or device operations under firmware control Full speed FS...

Page 209: ...rable via the CCM See Chapter 11 Chip Configuration Module CCM for more information The primary function of the transceiver is the physical signal conditioning of the external USB DP and DM cable signals for a USB 2 0 network Several USB system elements are not supported on the device as they are available via standard products from various manufacturers 10 1 2 Block Diagram Figure 10 1 shows the ...

Page 210: ...se features Complies with USB specification rev 2 0 USB host mode Supports enhanced host controller interface EHCI Allows direct connection of FS LS devices without an OHCI UHCI companion controller Supported by Linux and other commercially available operating systems USB device mode Supports full speed operation via the on chip transceiver Supports full speed high speed operation via an external ...

Page 211: ...t field Speed selection is auto detected at connect time via sensing of the DP or DM pull up resistor on the connected device using enumeration procedures in the USB network The USB OTG module provides these operation modes USB disabled In this mode the USB OTG s datapath does not accept transactions received on the USB interface USB enabled In this mode the USB host s datapath is enabled to accep...

Page 212: ...peed transceiver for the USB OTG module State Meaning Asserted Data 1 Negated Data 0 Timing Asynchronous USB_DP I O Data plus Output of dual speed transceiver for the USB OTG module State Meaning Asserted Data 1 Negated Data 0 Timing Asynchronous USB_PULLUP O Enables an external pull up on the USB_DP line This signal is controlled by the UOCSR BVLD bit State Meaning Asserted Pull up enabled UOCSR ...

Page 213: ...I_NXT I Next data PHY asserts ULPI_NXT to throttle data When USB port sends data to the PHY ULPI_NXT indicates when PHY accepts the current byte The USB port places the next byte on the data bus in the following clock cycle When the PHY sends data to USB port ULPI_NXT indicates when a new byte is available for USB port to consume State Meaning Asserted PHY is ready to transfer byte Negated PHY is ...

Page 214: ...sistor pull up on DP R Y A Session Valid AVLD Indicates a valid session level for A device detected on VBUS R W N B Session Valid BVLD Indicates a valid session level for B device detected on VBUS R W N Session Valid VVLD Indicates valid operating level on VBUS from USB device s perspective R W N Session End SEND Indicates VBUS fell below the session valid threshold R W N VBUS Fault PWRFLT Indicat...

Page 215: ...0100 10 3 3 1 10 14 0xFC0B_0103 Capability Register Length CAPLENGTH Y H D 8 R 0x40 10 3 3 2 10 15 0xFC0B_0104 Host Structural Parameters HCSPARAMS Y H 32 R 0x0001_0011 10 3 3 3 10 15 0xFC0B_0108 Host Capability Parameters HCCPARAMS Y H 32 R 0x0000_0006 10 3 3 4 10 16 0xFC0B_0122 Device Interface Version Number DCIVERSION N D 16 R 0x0001 10 3 3 5 10 17 0xFC0B_0124 Device Capability Parameters DCCP...

Page 216: ...nitialization EPPRIME N D 32 R W 0x0000_0000 10 3 4 18 10 41 0xFC0B_01B4 Endpoint De initialize EPFLUSH N D 32 R W 0x0000_0000 10 3 4 19 10 42 0xFC0B_01B8 Endpoint Status Register EPSR N D 32 R 0x0000_0000 10 3 4 20 10 42 0xFC0B_01BC Endpoint Complete EPCOMPLETE N D 32 R W 0x0000_0000 10 3 4 21 10 43 0xFC0B_01C0 Endpoint Control Register 0 EPCR0 N D 32 R W 0x0080_0080 10 3 4 22 10 44 0xFC0B_01C4 E...

Page 217: ... 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SM PHYM PHYW 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 1 Figure 10 4 General Hardware Parameters Register HWGENERAL Table 10 6 HWGENERAL Field Descriptions Field Description 31 11 Reserved always cleared 10 9 SM Serial mode Indicates presence of serial interface Always 11 11 Serial engine is present and defaulte...

Page 218: ...anslator periodic contexts Number of supported transaction translator periodic contexts Always 0x10 0x10 16 23 16 TTASY Transaction translator contexts Number of transaction translator contexts Always 0x02 0x02 2 15 4 Reserved always cleared 3 1 NPORT Indicates number of ports in host mode minus 1 Always 0 for the USB OTG module 0 HC Indicates module is host capable Always set Address 0xFC0B_000C ...

Page 219: ...ule 0 Store device transmit contexts in the TX FIFO 1 Store device transmit contexts in a register file 30 24 Reserved always cleared 23 16 TXCHANADD Transmit channel address Number of address bits required to address one channel s worth of TX data Always 0x04 15 8 TXADD Transmit address Number of address bits for the entire TX buffer Always 0x06 7 0 TXBURST Transmit burst Indicates number of data...

Page 220: ...LD Table 10 11 GPTIMERnLD Field Descriptions Field Description 31 24 Reserved must be cleared 23 0 GPTLD Specifies the value to be loaded into the countdown timer on a reset The value in this register represents the time in microseconds minus 1 for the timer duration For example for a one millisecond timer load 1000 1 999 0x00_03E7 Note Maximum value of 0xFF_FFFF or 16 777215 seconds Address 0xFC0...

Page 221: ...ister 29 25 Reserved must be cleared 24 MODE Timer mode Selects between a single timer countdown and a looped countdown In one shot mode the timer counts down to zero generates an interrupt and stops until the counter is reset by software In repeat mode the timer counts down to zero generates an interrupt and automatically reloads the counter and begins another countdown 0 One shot 1 Repeat 23 0 G...

Page 222: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 N_TT N_PTT 0 0 0 PI N_CC N_PCC 0 0 0 PPC N_PORTS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 Figure 10 13 Host Controller Structural Parameters Register HCSPARAMS Table 10 15 HCSPARAMS Field Descriptions Field Description 31 28 Reserved always cleared 27 24 N_TT Number of transaction translators Non EHCI field Indicates nu...

Page 223: ... PFL ADC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Figure 10 14 Host Controller Capability Parameters Register HCCPARAMS Table 10 16 HCCPARAMS Field Descriptions Field Description 31 16 Reserved always cleared 15 8 EECP EHCI extended capabilities pointer This optional field indicates the existence of a capabilities list 0x00 No extended capabilities are implemented Th...

Page 224: ...t is always physically contiguous 0 ADC 64 bit addressing capability This field is always 0 64 bit addressing is not supported 0 Data structures use 32 bit address memory pointers Address 0xFC0B_0122 DCIVERSION Access User read only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DCIVERSION W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 10 15 Device Controller Interface Version Register DCIVERSION Table 1...

Page 225: ...0 0 0 0 0 0 ITC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FS2 ATDTW SUTW 0 ASPE 0 ASP 0 IAA ASE PSE FS1 FS0 RST RS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10 17 USB Command Register USBCMD Table 10 19 USBCMD Field Descriptions Field Description 31 24 Reserved must be cleared 23 16 ITC Interrupt threshold control System software uses this field to set th...

Page 226: ...d 6 IAA Interrupt on async advance doorbell Used as a doorbell by software to tell controller to issue an interrupt the next time it advances the asynchronous schedule Software must write a 1 to this bit to ring the doorbell When controller has evicted all appropriate cached schedule states it sets USBSTS AAI register If the USBINTR AAE bit is set the host controller asserts an interrupt at the ne...

Page 227: ... is not in an attached state before initiating a device controller reset all primed endpoints must be flushed and the USBCMD RS bit must be cleared 0 RS Run Stop Host mode When set the controller proceeds with the execution of the schedule The controller continues execution as long as this bit is set When this bit is cleared the controller completes the current transaction on the USB and then halt...

Page 228: ... and the TD was from the asynchronous schedule This bit is also set by the host controller when a short packet is detected and the packet is on the asynchronous schedule A short packet is when the actual number of bytes received was less than the expected number of bytes Note This bit is not used by the device controller and is always zero 17 Reserved must be cleared 16 NAKI NAK interrupt Set by h...

Page 229: ...set at an interval of 1 ms during the prelude to the connect and chirp 6 URI USB reset received A non EHCI bit When the controller detects a USB reset and enters the default state this bit is set Software can write a 1 to this bit to clear it Used only by in device mode 0 No reset received 1 Reset received 5 AAI Interrupt on async advance By setting the USBCMD IAA bit system software can force the...

Page 230: ...I USB error interrupt When completion of USB transaction results in error condition the controller sets this bit If the TD on which the error interrupt occurred also had its interrupt on complete IOC bit set this bit is set along with the USBINT bit See Section 4 15 1 in the EHCI specification for a complete list of host error interrupt conditions See Table 10 58 for more information on device err...

Page 231: ...st be cleared 16 NAKE NAK interrupt enable When this bit and the USBSTS NAKI bit are set an interrupt generates 0 Disabled 1 Enabled 15 11 Reserved must be cleared 10 ULPIE ULPI enable When this bit and USBSTS ULPII are set controller issues an interrupt The interrupt is acknowledged by writing a 1 to USBSTS ULPII 9 Reserved must be cleared 8 SLE Sleep DC suspend enable A non EHCI bit When this bi...

Page 232: ...c microframe 4 SEE System error enable When this bit and the USBSTS SEI bit are set controller issues an interrupt Software clearing the USBSTS SEI bit acknowledges the interrupt 0 Disabled 1 Enabled 3 FRE Frame list rollover enable When this bit and the USBSTS FRI bit are set controller issues an interrupt Software clearing the USBSTS FRI bit acknowledges the interrupt Used only in host mode 0 Di...

Page 233: ...criptions Field Description 31 14 Reserved must be cleared 13 0 FRINDEX Frame index The value in this register increments at the end of each time frame microframe Bits N 3 are for the frame list current index This means each location of the frame list is accessed 8 times per frame once each microframe before moving to the next index In device mode the value is the current frame number of the last ...

Page 234: ...ode it is the ASYNCLISTADDR register in device mode it is the EPLISTADDR register See Section 10 3 4 8 Endpoint List Address Register EPLISTADDR for more information Table 10 24 PERIODICLISTBASE Field Descriptions Field Description 31 12 PERBASE Base Address These bits correspond to memory address signal 31 12 Used only in the host mode 11 0 Reserved must be cleared Address 0xFC0B_0154 DEVICEADDR ...

Page 235: ...escription 31 5 ASYBASE Link pointer low LPL These bits correspond to memory address signal 31 5 This field may only reference a queue head QH Used only in host mode 4 0 Reserved must be cleared Address 0xFC0B_0158 EPLISTADDR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EPBASE 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 236: ...ved must be cleared 30 24 TTHA TT Hub Address This field is used to match against the Hub Address field in a QH or siTD to determine if the packet is routed to the internal TT for directly attached FS LS devices If the hub address in the QH or siTD does not match this address then the packet is broadcast on the high speed ports destined for a downstream HS hub with the address in the QH or siTD 23...

Page 237: ... minimize back offs Address 0xFC0B_0164 TXFILLTUNING Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 TXFIFOTHRES 0 0 0 TXSCHHEALTH TXSCHOH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10 27 Transmit FIFO Tuning Controls TXFILLTUNING Table 10 30 TXFILLTUNING Field Descriptions Field ...

Page 238: ...ue chosen for this register should limit the number of back off events captured in the TXSCHHEALTH field to less than 10 per second in a highly utilized bus Choosing a value too high for this register is not desired as it can needlessly reduce USB utilization The time unit represented in this register is 1 267 s when a device connects in high speed mode The time unit represented in this register i...

Page 239: ... interrupt defined in the USBSTS and USBINTR registers When a wake up or read write operation completes the ULPI interrupt is set Table 10 31 ULPI VIEWPORT Field Descriptions Field Description 31 ULPI_WU ULPI wake up Setting this bit begins the wake up operation This bit automatically clears after the wake up is complete After this bit is set it can not be cleared by software Note The driver must ...

Page 240: ...tatus port reset suspend and current connect status It is also used to initiate test mode or force signaling and allows software to place the PHY into low power suspend mode and disable the PHY clock Address 0xFC0B_0180 CONFIGFLAG Access User read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 241: ...n be placed into low power suspend when downstream device is put into suspend mode or when no downstream device connects Software completely controls low power suspend Device mode For the USB OTG module in device mode the PHY can be put into low power suspend when the device is not running USBCMD RS 0 or suspend signaling is detected on the USB The PHCD bit is cleared automatically when the resume...

Page 242: ...P 0 it is non functional and does not report attaches detaches etc When an over current condition is detected on a powered port the host controller driver from a 1to a 0 removing power from the port transitions the PP bit in each affected port 11 10 LS Line status Reflects current logical levels of the USB DP bit 11 and DM bit 10 signal lines In host mode the line status by the host controller dri...

Page 243: ...er the resume duration is timed in the driver When the controller owns the port the resume sequence follows the defined sequence documented in the USB Specification Revision 2 0 The resume signaling full speed K is driven on the port as long as this bit remains set This bit remains set until the port switches to the high speed idle Clearing this bit has no affect because the port controller times ...

Page 244: ...he bit status does not change until the port state actually changes There may be a delay in disabling or enabling a port due to other host and bus events When the port is disabled downstream propagation of data is blocked except for reset This field is cleared if the PP bit is cleared in host mode Device mode The device port is always enabled This bit is set 1 CSC Connect change status Host mode T...

Page 245: ... 1MSE 1 millisecond timer interrupt enable 0 Disable 1 Enable 28 BSEIE B session end interrupt enable 0 Disable 1 Enable 27 BSVIE B session valid interrupt enable 0 Disable 1 Enable 26 ASVIE A session valid interrupt enable 0 Disable 1 Enable 25 AVVIE A VBUS valid interrupt enable 0 Disable 1 Enable 24 IDIE USB ID interrupt enable 0 Disable 1 Enable 23 Reserved must be cleared 22 DPIS Data pulse i...

Page 246: ...cted on port 13 1MST 1 millisecond timer toggle This bit toggles once per millisecond 12 BSE B session end 0 VBus is above B session end threshold 1 VBus is below B session end threshold 11 BSV B Session valid 0 VBus is below B session valid threshold 1 VBus is above B session valid threshold 10 ASV A Session valid 0 VBus is below A session valid threshold 1 VBus is above A session valid threshold...

Page 247: ...f ensuring the TX latency fills to capacity before the packet launches onto the USB Time duration to pre fill the FIFO becomes significant when stream disable is active See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature Also in systems with high system bus utilization setting this bit ensures no overruns or underruns during operation at the expense of...

Page 248: ...dle default for the USB OTG module 01 Reserved 10 Device controller 11 Host controller Note The USB OTG module must be initialized to the desired operating mode after reset Address 0xFC0B_01AC EPSETUPSR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPSETUPSTAT W Reset 0 0 0 0 0 ...

Page 249: ... the corresponding bit when posting a new transfer descriptor to an endpoint Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer Hardware clears this bit when associated endpoint s is are successfully primed Note These bits are momentarily set by hardware during hardware re priming operations when a dTD retires and th...

Page 250: ...must be cleared 3 0 ERBR Endpoint receive buffer ready One bit for each endpoint indicates status of the respective endpoint buffer The hardware sets this bit in response to receiving a command from a corresponding bit in the EPPRIME register A constant delay exists between setting a bit in the EPPRIME register and endpoint indicating ready This delay time varies based upon the current USB traffic...

Page 251: ...0 0 0 TXT 0 TXS 0 0 0 0 0 0 0 0 RXE 0 0 0 RXT 0 RXS W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Figure 10 38 Endpoint Control 0 EPCR0 Table 10 41 EPCR0 Field Descriptions Field Description 31 24 Reserved must be cleared 23 TXE TX endpoint enable Endpoint zero is always enabled 1 Enable 22 20 Reserved must be cleared 19 18 TXT TX endpoint type Endpoint zero is always a c...

Page 252: ... W TXR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 RXE 0 RXI 0 RXT RXD RXS W RXR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10 39 Endpoint Control Registers EPCRn Table 10 42 EPCRn Field Descriptions Field Description 31 24 Reserved must be cleared 23 TXE TX endpoint enable 0 Disabled 1 Enabled 22 TXR TX data toggle reset When a configuration eve...

Page 253: ... a 1 to this bit to synchronize the data PIDs between the host and device This bit is self clearing 5 RXI RX data toggle inhibit This bit is only for testing and should always be written as 0 Writing a 1 to this bit causes this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID 0 PID sequencing enabled 1 PID sequencing disabled 4 Reserved must b...

Page 254: ... data structures are similar to those in the EHCI specification and used to allow device responses to be queued for each of the active pipes in the device 10 4 3 FIFO RAM Controller The FIFO RAM controller is used for context information and to control FIFOs between the protocol engine and the DMA controller These FIFOs decouple the system processor memory bus requests from the extremely tight tim...

Page 255: ...o be disabled via the CCM and 15k external resistors to connect from DP and DM signals to ground 10 5 Initialization Application Information 10 5 1 Host Operation Enhanced Host Controller Interface EHCI Specification defines the general operational model for the USB module in host mode The EHCI specification describes the register level interface for a host controller for USB Revision 2 0 It inclu...

Page 256: ... schedule system software must write the ASYNCLISTADDR register with the address of a control or bulk queue head Software must then enable the asynchronous schedule by setting the asynchronous schedule enable ASE bit in the USBCMD register To communicate with devices via the periodic schedule system software must enable the periodic schedule by setting the periodic schedule enable PSE bit in the U...

Page 257: ... and continues through the end of the buffer pointers longwords After a transfer is complete the dTD status longword updates in the dTD pointed to by the currentTD pointer While a packet is in progress the overlay area of the dQH acts as a staging area for the dTD so the device controller can access needed information with minimal latency Figure 10 41 shows the endpoint queue head structure Endpoi...

Page 258: ...MultO 0 0 Status 0x0C1 Buffer Pointer Page 0 Current Offset 0x101 Buffer Pointer Page 1 Reserved 0x141 Buffer Pointer Page 2 Reserved 0x181 Buffer Pointer Page 3 Reserved 0x1C1 Buffer Pointer Page 4 Reserved 0x201 Reserved 0x24 Setup Buffer Bytes 3 0 0x28 Setup Buffer Bytes 7 4 0x2C Device controller read write all others read only Figure 10 41 Endpoint Queue Head Layout Table 10 44 Endpoint Capab...

Page 259: ...t from the host to retire the current dTD Setting this bit disables the zero length packet When the device is transmitting the hardware does not append any zero length packet When receiving it does not require a zero length packet to retire a dTD whose last packet was equal to the maximum packet length packet The dTD is retired as soon as Total Bytes field goes to zero or a short packet is receive...

Page 260: ... Transfers with Transfer Descriptors 10 5 2 2 1 Next dTD Pointer Offset 0x0 The next dTD pointer is used to point the device controller to the next dTD in the linked list Table 10 46 Multiple Mode Control longword Field Description 1 31 0 Setup Buffer 0 Setup Buffer 0 This buffer contains bytes 3 to 0 of an incoming setup buffer packet and is written by the device controller software reads 2 31 0 ...

Page 261: ...mpletion of the transaction The maximum value software may store in the field is 5 4K 0x5000 This is the maximum number of bytes 5 page pointers can access Although possible to create a transfer up to 20K this assumes the first offset into the first page is 0 When the offset cannot be predetermined crossing past the fifth page can be guaranteed by limiting the total bytes to 16K Therefore the maxi...

Page 262: ... last transaction performed on this dTD The bit encodings are Bit Status Field Description 7 Active Set by software to enable the execution of transactions by the device controller 6 Halted Set by the device controller during status updates to indicate a serious error has occurred at the device endpoint addressed by this dTD Any time a transaction results in the halted bit being set the active bit...

Page 263: ...te value to the USBINTR to enable the desired interrupts For device operation setting UE UEE PCE URE and SLE is recommended For a list of available interrupts refer to Section 10 3 4 3 USB Interrupt Enable Register USBINTR and Section 10 3 4 2 USB Status Register USBSTS 5 Set the USBMODE CM field to enable device mode and set the USBMODE ES bit for big endian operation 6 Optionally write the USBCM...

Page 264: ... Specification Revision 2 0 Figure 10 43 depicts the state of a USB 2 0 device Figure 10 43 USB 2 0 Device States States powered attach defaultFS HS suspendFS HS are implemented in the USB OTG and they are communicated to the DCD using these status bits Default FS HS Suspend FS HS Address FS HS Suspend FS HS Configured FS HS Suspend FS HS Attach Powered Bus Inactive Bus Activity Bus Inactive Bus A...

Page 265: ...setup token semaphores by reading the EPSETUPSR register and writing the same value back to the EPSETUPSR register 2 Clear all the endpoint complete status bits by reading the EPCOMPLETE register and writing the same value back to the EPCOMPLETE register 3 Cancel all primed status by waiting until all bits in the EPPRIME are 0 and then writing 0xFFFF_FFFF to EPFLUSH 4 Read the reset bit in the POR...

Page 266: ...by using electrical signaling to indicate remote wake up The ability of a device to signal remote wake up is optional The USB OTG is capable of remote wake up signaling When the USB OTG is reset remote wake up signaling must be disabled Suspend Operational Model The USB OTG moves into the suspend state when suspend signaling is detected or activity is missing on the upstream port for more than a s...

Page 267: ...number of endpoints required for device operation The only exception is that control endpoints must use both directions on a single endpoint number to function as a control endpoint Endpoint 0 for example is always a control endpoint and uses both directions Each endpoint direction requires a queue head allocated in memory If the maximum is four endpoint numbers one for each endpoint direction use...

Page 268: ...ite to the EPCRn register can ensure both stall bits are set at the same instant NOTE Any write to the EPCRn register during operational mode must preserve the endpoint type field perform a read modify write 10 5 3 3 3 Data Toggle Data toggle maintains data coherency between host and device for any given data pipe For more information on data toggle refer to the USB 2 0 specification Data Toggle R...

Page 269: ...For example if endpoint 3 transmit direction is configured as a bulk pipe expect the host to send IN requests to that endpoint This USB OTG module prepares packets for each endpoint direction in anticipation of the host request The process of preparing the device controller to send or receive data in response to host initiated transaction on the bus is referred to as priming the endpoint This term...

Page 270: ...TD is retired by the device controller when the packets described in the transfer descriptor are completed Each dTD describes N packets to transfer according to the USB variable length transfer protocol The formula below and Table 10 53 describe how the device controller computes the number and length of the packets sent received by the USB vary according to the total number of bytes and maximum p...

Page 271: ... allows transfers larger than the total bytes field spanning across two or more dTDs Upon successful completion of the packet s described by the dTD the active bit in the dTD is cleared and the next pointer is followed when the terminate bit is clear When the terminate bit is set USB OTG flushes the endpoint direction and ceases operations for that endpoint direction Upon unsuccessful completion o...

Page 272: ...byte array copy and execute status handshake phases NOTE After receiving a new setup packet status and or handshake phases may remain pending from a previous control sequence These should be flushed and de allocated before linking a new status and or handshake dTD for the most recent setup packet Data Phase Following the setup phase the DCD must create a device transfer descriptor for the data pha...

Page 273: ...ontrol endpoint according to the device controller state 10 5 3 4 5 Isochronous Endpoint Operation Isochronous endpoints used for real time scheduled delivery of data and their operational model is significantly different than the host throttled bulk interrupt and control data pipes Real time delivery by the USB OTG is accomplished by Exactly MULT packets per micro frame are transmitted received T...

Page 274: ...to the design the device controller hardware masks that prime start until the next frame boundary This behavior is hidden from the DCD but occurs so the device controller can match the dTD to a specific micro frame Another difference with isochronous endpoints is that the transaction must wholly complete in a micro frame After an ISO transaction is started in a micro frame it retires the correspon...

Page 275: ...e device controller by at least two micro frames Isochronous Pipe Synchronization When it is necessary to synchronize an isochronous data pipe to the host the micro frame number FRINDEX register can act as a marker To cause a packet transfer to occur at a specific micro frame number N the DCD must interrupt on SOF during frame N 1 When the FRINDEX equals N 1 the DCD must write the prime bit The US...

Page 276: ...he dTD is retired see Section 10 5 3 6 1 Software Link Pointers Figure 10 44 Endpoint Queue Head Diagram In addition to current and next pointers and the dTD overlay examined in Section 10 5 3 4 Packet Transfers the dQH also contains the following parameters for the associated endpoint multipler maximum packet length and interrupt on setup The next section includes demonstration of complete initia...

Page 277: ...pecial treatment by the DCD A setup transfer does not use a dTD but instead stores the incoming data from a setup packet in an 8 byte buffer within the dQH Upon receiving notification of the setup packet the DCD should manage the setup transfer by 1 Copying setup buffer contents from dQH RX to software buffer 2 Acknowledging setup backup by writing a 1 to the corresponding bit in the EPSETUPSR reg...

Page 278: ...rs NOTE Check the status of each dTD to determine completed status 10 5 3 6 2 Building a Transfer Descriptor Before a transfer can be executed from the linked list a dTD must be built to describe the transfer Use the following procedure for building dTDs Allocate an 8 longword dTD block of memory aligned to 8 longword boundaries The last 5 bits of the address must equal 00000 Write the following f...

Page 279: ...o 3 If set continue to 6 6 Clear the USBCMD ATDTW bit 7 If status bit read in step 4 is 1 DONE 8 If status bit read in step 4 is 0 then go to case 1 step 1 10 5 3 6 4 Transfer Completion After a dTD is initialized and the associated endpoint is primed the device controller executes the transfer upon the host initiated request The DCD is notified with a USB interrupt if the interrupt on complete bi...

Page 280: ...n the USB bus activity It is not desirable to have this wait loop within an interrupt service routine 3 Read the EPSR register to ensure that for all endpoints commanded to be flushed that the corresponding bits are now cleared If the corresponding bits are set after step 2 has finished flush failed as described below In very rare cases a packet is in progress to the particular endpoint when comma...

Page 281: ... of packets defined in the dQH mult field within the given micro frame For scheduled data delivery DCD may need to readjust the data queue because a fulfillment error causes the device controller to cease data transfers on the pipe for one micro frame During the dead micro frame the device controller reports error on the pipe and primes for the following frame Table 10 60 Interrupt Managing Order ...

Page 282: ...ation Device and OTG operation are not specified in the EHCI specification and thus the implementation supported in the USB OTG module is proprietary 10 5 5 1 Embedded Transaction Translator Function The USB host mode supports directly connected full and low speed devices without requiring a companion controller by including the capabilities of a USB 2 0 high speed hub transaction translator Altho...

Page 283: ...ugh the root hub It is demonstrated here how hub address and endpoint speed fields should be set for directly attached FS LS devices and hubs 1 QH for direct attach FS LS asynchronous bulk control endpoints periodic interrupt Hub address equals 0 Transactions to direct attached device hub Table 10 63 Functional Differences Between EHCI and EHCI with Embedded TT Standard EHCI EHCI with embedded Tra...

Page 284: ...ons assume the reader is familiar with the EHCI and USB 2 0 transaction translator operational models Microframe Pipeline The EHCI operational model uses the concept of H frames and B frames to describe the pipeline between the host H and the bus B The embedded transaction translator uses the same pipeline algorithms specified in the USB 2 0 specification for a hub based transaction translator All...

Page 285: ...ull low speed packet babbles into SOF time USB 2 0 11 17 4 Transaction tracking for 2 data pipes USB 2 0 11 17 5 Clear_TT_Buffer capability provided though the use of the TTCTRL register Periodic Transaction Scheduling and Buffer Management The following USB 2 0 specification items are implemented in the embedded transaction translator USB 2 0 11 18 6 1 2 Abort of pending start splits EOF and not ...

Page 286: ...USB OTG module in the operation registers should always be written to zero This is an EHCI requirement of the device controller driver that must be adhered to Read operations by the module must properly mask EHCI reserved fields some of which are device fields in the USB OTG module registers 10 5 5 4 SOF Interrupt The SOF interrupt is a free running 125 µs interrupt for host mode EHCI does not spe...

Page 287: ... the device Software shall clear the PORTSCn PR bit after 10 ms This step necessary in a standard EHCI design may be omitted with this implementation Should the EHCI host controller driver attempt to write a 0 to the reset bit while a reset is in progress the write is ignored and the reset continues until completion Port change interrupt Port enable change occurs to notify the host controller that...

Page 288: ...itates serial boot See Chapter 12 Serial Boot Facility SBF for details 11 1 3 Modes of Operation The only chip operating mode available on this device is master mode In master mode the ColdFire core can access external memories and peripherals The external bus consists of a 32 bit data bus and 24 address lines The available bus control signals include R W TS TA OE and BE BWE 3 0 Up to four chip se...

Page 289: ...ster Definition The CCM programming model consists of the registers listed in the below table Table 11 1 Signal Properties Name Function Reset State BOOTMOD 1 0 Reset configuration select FB_AD 7 0 Reset configuration override pins Table 11 2 BOOTMOD 1 0 Values BOOTMOD 1 0 Meaning 00 Boot from Flexbus with defaults 01 Reserved 10 Boot from Flexbus and override defaults via data bus FB_AD 7 0 11 Bo...

Page 290: ...n the Go Controller Status Register UOCSR 16 R W 0x0010 11 3 6 11 11 0xFC0A_0018 Serial Boot Facility Status Register SBFSR 2 16 R See Section 12 3 1 12 3 0xFC0A_0020 Serial Boot Facility Control Register SBFCR 2 16 R W See Section 12 3 2 12 3 1 User access to supervisor only address locations have no effect and result in a bus error 2 See Chapter 12 Serial Boot Facility SBF for details Address 0x...

Page 291: ...PLLMODE PLL mode Reflects the chosen overall clocking mode for the device 0 Normal operation PLL drives internal clocks 1 Limp mode low power clock divider drives internal clocks 3 PCIMODE FBCONFIG 011 111 PCI host agent mode if the PCI is enabled Reflects whether the PCI is a host or agent 0 PCI is agent 1 PCI is host 3 OSCMODE FBCONFG 011 111 Oscillator clock mode if the PCI is disabled 0 Crysta...

Page 292: ... boot because serial boot reset configuration can select reference clock multipliers not shown in directly above The PLL output frequency can also be programmed after reset via the PLL output divider registers PODR and PLL feedback divider register PFDR See Chapter 8 Clock Module for more details The default output divider settings values used to divide the VCO clock down to the system clocks are ...

Page 293: ...s port size configuration Relects the chosen Flexbus address data muxing mode and port size Muxed means that the FB_AD 31 0 signals are used for Flexbus address and data Non muxed means that the FB_AD 31 0 signals are used for Flexbus data and the PCI_AD 23 0 signals are used for Flexbus address Note The FBCONFIG field value may not be valid following serial boot because serial boot reset configur...

Page 294: ...on 3 OSCMODE Oscillator clock mode 0 Crystal oscillator mode 1 Oscillator bypass mode 2 0 PLLMULT PLL clock mode Reflects the chosen PLL clock mode as set by the reference clock multiplier used to generate the VCO clock Note The PLLMULT field value may not be valid following serial boot because serial boot reset configuration can select reference clock multipliers not shown in the above table The ...

Page 295: ...cess Supervisor read only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 1 1 FBCONFIG PLL MODE OSC MODE PLLMULT W Reset 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 Figure 11 5 Reset Configuration Register RCON 256 pin Address 0xFC0A_000A CIR Access Supervisor read only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PIN PRN W Reset Device Dependent Mask Set Dependent Figure 11 6 Chip Identification Register CIR ...

Page 296: ...05 USBPUD 0 0 0 USBOC 1 1 SBF_RCON 108 USBSRC 1 1 SBF_RCON 109 Table 11 8 MISCCR Field Descriptions Field Description 15 13 Reserved must be cleared 12 LIMP Limp mode enable Selects between the PLL and the low power clock divider as the source of all system clocks 0 Normal operation PLL drives system clocks 1 Limp mode low power clock divider drives system clocks Note The transient behavior of the...

Page 297: ...imer DMA signals and SSI DMA signals as those signals are mapped to DMA channels 9 12 Refer to the Chapter 19 Enhanced Direct Memory Access eDMA for more details on the DMA controller 0 SSI RX0 SSI RX1 SSI TX0 and SSI TX1 DMA signals mapped to DMA channels 9 12 respectively 1 Timer 0 3 DMA signals mapped to DMA channels 9 12 respectively 4 SSISRC SSI clock source Selects between the PLL and the ex...

Page 298: ...es the divide value used to produce the system clocks during limp mode A 2 1 ratio is maintained between the core and the internal bus This field is used only when MISCCR LIMP bit is set Eqn 11 1 Note When LPDIV is cleared divide by 1 the internal bus clock and FB_CLK do not have a 50 50 duty cycle 7 0 SSIDIV SSI oversampling clock divider Specifies the divide value used to produce the oversamplin...

Page 299: ...if the session for a B peripheral is valid 0 Session is not valid for a B peripheral 1 Session is valid for a B peripheral 5 VVLD VBUS valid Indicates if voltage on VBUS is at a valid level for operation 0 Voltage level on VBUS is not valid for operation 1 Voltage level on VBUS is valid for operation 4 SEND Session end Indicates if voltage on VBUS has dropped below the session end threshold 0 Volt...

Page 300: ...figuration BOOTMOD 1 0 10 If the BOOTMOD pins are 10 during reset the chip configuration after reset is determined according to the levels driven onto the FB_AD 7 0 pins See Table 11 12 The internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration NOTE The logic levels for reset configuration on FB_AD 7 0 must be actively d...

Page 301: ... addr data 8 bit boot 000 No PCI non muxed FB addr data 32 bit boot FB_AD 31 0 PCI_ See RCON 7 5 FB_AD 7 5 Flexbus PCI Port Size Mode 256 pin Devices 111 Reserved 110 No PCI muxed FB addr data 16 bit boot 101 No PCI muxed FB addr data 8 bit boot 100 No PCI muxed FB addr data 32 bit boot 011 Reserved 010 No PCI non muxed FB addr data 16 bit boot 001 No PCI non muxed FB addr data 8 bit boot 000 No P...

Page 302: ... 010 VCO 24 x REF 001 VCO 10 x REF 000 VCO 20 x REF none See RCON 1 0 FB_AD 1 0 PLL Multiplier 360 pin PCI Enabled Devices 11 VCO 8 x REF CPU 266 200 PCI 66 50 10 VCO 16 x REF CPU 266 200 PCI 33 25 01 VCO 6 x REF CPU 200 180 PCI 66 50 00 VCO 12 x REF CPU 200 240 PCI 33 40 1 Modifying the default configurations through the FB_AD 7 0 pins is possible only if the external BOOTMOD 1 0 pins are 10 whil...

Page 303: ...bit port FB_AD 31 0 configured for GPIO 10 8 bit port 01 16 bit port 00 32 bit port PCI_AD 31 0 360 pin See RCON 7 5 SBF_RCON 125 PCI and Flexbus A D Pin Mode 1 PCI disabled Flexbus non muxed address data mode 0 PCI enabled Flexbus muxed address data mode none See RCON 3 SBF_RCON 124 Oscillator Mode 1 Oscillator bypass mode 0 Crystal oscillator mode none See MISCCR 11 SBF_RCON 123 Bus Monitor Enab...

Page 304: ...8 USB VBUS Overcurrent Sense Polarity 1 USB_VBUS_OC is active high 0 USB_VBUS_OC is active low none See MISCCR 7 SBF_RCON 107 SSI RXD TXD Pull Enable 1 SSI_RXD SSI_TXD pull cells enabled 0 SSI_RXD SSI_TXD pull cells disabled none See MISCCR 6 SBF_RCON 106 SSI RXD TXD Pull Select 1 SSI_RXD SSI_TXD pulled high 0 SSI_RXD SSI_TXD pulled low none See MISCCR 4 SBF_RCON 105 SSI Clock Source 1 PLL drives ...

Page 305: ...sabled none See RCON 3 host mode enables BAR SBF_RCON 98 PCI BAR2 Enable 1 BAR2 enabled 0 BAR2 disabled none See RCON 3 host mode enables BAR SBF_RCON 97 PCI BAR1 Enable 1 BAR1 enabled 0 BAR1 disabled none See RCON 3 host mode enables BAR SBF_RCON 96 PCI BAR0 Enable 1 BAR0 enabled 0 BAR0 disabled none 5807 SBF_RCON 95 80 PCI Device ID none 1957 SBF_RCON 79 64 PCI Vendor ID none 068000 SBF_RCON 63 ...

Page 306: ...e RCON 7 5 SBF_RCON 127 126 Boot Port Size 11 0 bit port FB_AD 31 0 configured for GPIO 10 8 bit port 01 16 bit port 00 32 bit port PCI_AD 23 0 See RCON 7 5 SBF_RCON 125 Flexbus A D Pin Mode 1 Flexbus non muxed address data mode 0 Flexbus muxed address data mode none See RCON 3 SBF_RCON 124 Oscillator Mode 1 Oscillator bypass mode 0 Crystal oscillator mode none See MISCCR 11 SBF_RCON 123 Bus Monit...

Page 307: ...dress 0x0000_0004 causes the processor to start executing from external memory space decoded by FB_CS0 11 4 3 Low Power Configuration After reset the device can be configured for operation during the low power modes using the low power control register LPCR For more information on this register see Section 9 2 5 Low Power Control Register LPCR ...

Page 308: ... 1 SBF Block Diagram 12 1 1 Overview The SBF interfaces to an external SPI memory to read configuration data and boot code during the processor reset sequence if BOOTMOD 1 0 equals 11 By reading data stored in the SPI memory the SBF adjusts the SPI memory clock frequency configures an extended set of power up options for the processor and optionally loads code into the on chip SRAM Through interac...

Page 309: ... listed below Table 12 1 Signal Properties Signal I O Description Reset Pull Up SBF_CK O Shift clock Alternate edges of this signal cause the SPI memory to accept data from and drive data to the processor SBF_CS O Chip select This signal enables the SPI memory and places it into an active state ready to accept commands SBF_DI I Data in The SPI memory drives and the processor accepts read data on t...

Page 310: ...0xFC0A_0020 SBFCR Access User read write once 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 FR BLDIV W Reset 0 0 0 0 0 0 0 0 0 0 0 01 See Note 1 Reset value is 0 and is reset only by power on reset remains unchanged for other reset types Note The reset value is loaded from SPI memory during serial boot following power on reset It remains unchanged for other reset types Prior to thi...

Page 311: ...k divider Determines the SBF clock PLL input reference clock divisor that generates the serial shift clock output on SBF_CK Prior to the serial boot sequence a divisor of 67 is used During the serial boot sequence this field is loaded with the value read from the SPI memory The application may write to this register to change the divisor for any subsequent serial boot that follows a soft reset con...

Page 312: ...nd used for subsequent soft resets This speeds reboot for systems that do not benefit from the optional FAST_READ on soft reset feature e g the SPI memory does not support FAST_READ or the input reference clock does not exceed the maximum allowable frequency for the READ command 12 4 2 Reset Configuration and Optional Boot Load After the steps in Section 12 4 1 Serial Initialization and Shift Cloc...

Page 313: ... and maps it to address 0 via the RAMBAR before control of the processor is restored to the ColdFire core The reset vector initial stack pointer and program counter should point to locations in the on chip SRAM so that boot code can initialize the device and load the application software from the SPI memory or via some other mechanism e g a hard disk drive connected to the ATAPI controller or a ne...

Page 314: ...mode After a soft reset 0x12 4 BLL 1 1 CODE_BYTE_ 4 BLL 1 1 1 This assumes SBFSR PLL is non zero If PLL is zero the SBF does not access data at these addresses 2 Start of user code copied into the on chip SRAM CODE_BYTE_0 3 is the supervisor stack pointer SP when loading completes CODE_BYTE_4 7 is the program counter PC when loading completes Table 12 6 SPI Memory Organization 256 pin Devices Byte...

Page 315: ... the SBF electrical specifications Specifically delays present throughout the system including those between the SBF the pin multiplexing logic and the actual I O pads effectively limit the maximum frequency at which the SBF operates and can preclude use of the FAST_READ feature altogether Even when the delays within the processor itself are minimized the actual SPI memories may have similarly unt...

Page 316: ...d is explained in these Figure 13 1 Reset Controller Block Diagram 13 1 2 Features Module features include the following Five sources of reset External Power on reset POR Core watchdog timer Phase locked loop PLL loss of lock Software Software assertable RSTOUT pin independent of chip reset state Software readable status flags indicating the cause of the last reset Power On Reset Core Watchdog Tim...

Page 317: ... Map Register Definition The reset controller programming model consists of these registers Reset control register RCR which selects reset control functions Reset status register RSR which reflects the state of the last reset source See Table 13 2 for the memory map and the following paragraphs for register descriptions 13 3 1 Reset Control Register RCR The RCR allows software control for requesti...

Page 318: ...e 7 6 5 4 3 2 1 0 R SOFTRST FRCRSTOUT 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 13 2 Reset Control Register RCR Table 13 3 RCR Field Descriptions Field Description 7 SOFTRST Allows software to request a reset The reset caused by setting this bit clears this bit 1 Software reset request 0 No software reset request 6 FRCRSTOUT Allows software to assert or negate the external RSTOUT pin 1 Assert RST...

Page 319: ...t caused by software 4 Reserved should be cleared 3 POR Power on reset flag Indicates power on reset caused the last reset 0 Last reset not caused by power on reset 1 Last reset caused by power on reset 2 EXT External reset flag Indicates that the last reset was caused by an external device or circuitry asserting the external RESET pin 0 Last reset not caused by external reset 1 Last reset caused ...

Page 320: ...external reset to be recognized asynchronously 13 4 1 3 Core Watchdog Timer Reset A core watchdog timer timeout causes the timer reset request to be recognized and latched If the RESET pin is negated and the PLL has acquired lock the reset controller asserts RSTOUT either for approximately 512 bus clock cycles non serial boot or for the duration of the serial boot sequence Then the device exits re...

Page 321: ... All cycle counts given are approximate N RESET Pin or WD Timeout or SW Reset Loss Of Lock RESET Negated BOOTMOD 1 0 10 PLL Locked Assert RSTOUT and Latch Reset Status Wait 512 FB_CLK Cycles Latch Configuration Negate RSTOUT Assert RSTOUT and Latch Reset Status Y Y 2 3 N N 1 5 6 10 11 Y Y N Y 12 4 11A 7 BOOTMOD 1 0 11 Y N 8 Serial Boot Serial Boot Sequence 9 Parallel RCON from FB_AD 7 0 pins Power...

Page 322: ...r the PLL to attain lock 7 before waiting either 512 bus clock cycles 10 or for the duration of serial boot 9 For non serial boot the reset control logic may then latch the chip configuration options from the FB_AD 7 0 pins 11 11A RSTOUT is then negated 12 If a loss of lock occurs during the 512 bus clock count 10 or during serial boot 9 the reset flow switches to 7 and waits for the PLL to lock b...

Page 323: ...Reset Controller Module 13 8 Freescale Semiconductor ...

Page 324: ...ncontrolled software loops via a special software service sequence If periodic software servicing action does not occur the CWT times out with a programmed response system reset or interrupt to allow recovery or corrective action to be taken Fault access reporting is also available within the SCM The user can use these registers during the resulting interrupt service routine and perform an appropr...

Page 325: ...32 R W 0x4440_4444 14 2 2 14 4 0xFC00_0040 Peripheral Access Control Register E PACRE 32 R W 0x4444_4444 14 2 2 14 4 0xFC00_0044 Peripheral Access Control Register F PACRF 32 R W 0x4444_4444 14 2 2 14 4 0xFC00_0048 Peripheral Access Control Register G PACRG 32 R W 0x4444_4444 14 2 2 14 4 0xFC04_0013 Wakeup Control Register WCR 1 1 The WCR register is described in Chapter 9 Power Management 8 R W 0...

Page 326: ...l Boot 3 2 1 0 R 0 MTR MTW MPL W Figure 14 2 MPROTn Fields Table 14 3 MPROTn Field Descriptions Field Description 3 Reserved must be cleared 2 MTR Master trusted for read Determines whether the master is trusted for read accesses 0 This master is not trusted for read accesses 1 This master is trusted for read accesses 1 MTW Master trusted for writes Determines whether the master is trusted for wri...

Page 327: ... 0 0 PACR15 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 Figure 14 4 Peripheral Access Control Register B PACRB Address 0xFC00_0028 PACRC Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PACR16 PACR17 PACR18 PACR19 0 0 0 0 PACR21 PACR22 PACR23 W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1...

Page 328: ...11 10 9 8 7 6 5 4 3 2 1 0 R PACR48 PACR49 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 Figure 14 9 Peripheral Access Control Register G PACRG Table 14 4 PACRn Assignments Slot Number PACRn Peripheral 0 PACR0 SCM MPR and PACRs 1 PACR1 Crossbar switch 2 PACR2 FlexBus 12 PACR12 FEC0 13 PACR13 FEC1 15 PACR15 Real Time Clock 16 ...

Page 329: ...P WP TP W Figure 14 10 PACRn Fields Table 14 5 PACRn Field Descriptions Field Description 3 Reserved must be cleared 2 SP Supervisor protect Determines whether the peripheral requires supervisor privilege level for access 0 This peripheral does not require supervisor privilege level for accesses 1 This peripheral requires supervisor privilege level for accesses The master privilege level must indi...

Page 330: ... is attempted by an untrusted master the access terminates with an error response and no peripheral access initiates Address 0xFC04_0016 CWCR Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RO 0 0 0 0 0 0 CW RWH CWE CWRI CWT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14 11 Core Watchdog Control Register CWCR Table 14 6 CWCR Field Descriptions Field Description 15 RO Read only co...

Page 331: ...irst time out generates an interrupt to the processor and if not serviced a second time out generates a system reset and sets the RSR WDRCORE flag in the reset controller 10 If a time out occurs the CWT generates a system reset and RSR WDRCORE in the reset controller is set 11 The CWT functions in a window mode of operation For this mode the servicing of the CWSR must occur during the last 25 of t...

Page 332: ...3 SCM Interrupt Status Register SCMISR Table 14 7 SCMISR Field Descriptions Field Description 7 2 Reserved must be cleared 1 CFEI Core fault error interrupt flag Indicates if a bus fault has occurred Writing a 1 clears this bit and negates the interrupt request Writing a 0 has no effect 0 No bus error 1 A bus error has occurred The faulting address attributes and possibly write data are captured i...

Page 333: ...ld Description 31 10 Reserved must be cleared 9 GBR Global burst enable for reads Allows bursts to happen on read transactions from the crossbar switch slaves to the USB On the Go module 0 Read bursts are disabled 1 Read bursts are enabled Note If GBR and GBW are cleared then SBE is ignored 8 GBW Global burst enable for writes Allows bursts to happen on write transactions to the crossbar switch sl...

Page 334: ...s the faulting address of the last core access terminated with an error response Address 0xFC04_0075 CFIER Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 ECFEI W Reset 0 0 0 0 0 0 0 0 Figure 14 16 Core Fault Interrupt Enable Register CFIER Table 14 10 CFIER Field Descriptions Field Description 7 1 Reserved must be cleared 0 ECFEI Enable core fault error interrupt 0 Do not generate an error...

Page 335: ...WRITE SIZE CACHE 0 MODE TYPE W Reset Figure 14 18 Core Fault Attributes Register CFATR Table 14 12 CFATR Field Descriptions Field Description 7 WRITE Indicates the direction of the last faulted core access 0 Core read access 1 Core write access 6 4 SIZE Indicates the size of the last faulted core access 000 8 bit core access 001 16 bit core access 010 32 bit core access Else Reserved 3 CACHE Indic...

Page 336: ...first checked to see if its privilege rights allow access to the given memory space If the privilege rights are correct the access proceeds on the internal bus If the privilege rights are insufficient for the targeted memory space the transfer is immediately aborted and terminated with an exception and the targeted module not accessed 14 3 2 Core Watchdog Timer The core watchdog timer CWT prevents...

Page 337: ...iate system reset regardless of the value in the CWCR CWRI field The timer value is constantly compared with the time out period specified by CWCR CWT and any write to the CWCR register resets the watchdog timer In addition a write once control bit in the CWCR sets the CWCR to read only to prevent accidental updates to this control register from changing the desired system configuration After this...

Page 338: ...x devices have up to seven masters and slaves 7Mx6S connected to the crossbar switch The seven masters are the ColdFire core eDMA controller FECs USB OTG module PCI controller and serial boot The slaves are SDRAM controller FlexBus SRAM controller ATA controller PCI controller backdoor and the peripheral bus controller Figure 15 1 is a block diagram of the MCF5445x family bus architecture showing ...

Page 339: ...acheable addresses e g ADDR 31 equals 0 identifies the cacheable space Table 15 1 Crossbar Switch Master Slave Assignments Master Modules Crossbar Port Module Master 0 M0 ColdFire core Master 1 M1 eDMA controller Master 2 M2 Fast Ethernet controller 0 Master 3 M3 Fast Ethernet controller 1 Master 5 M5 PCI controller Master 6 M6 USB On the Go Master 7 M7 Serial boot Slave Modules Crossbar Port Modu...

Page 340: ...ified in a wrap around manner to give all masters fair access to the slave See Section 15 5 1 2 Round Robin Priority Operation 15 4 Memory Map Register Definition Two registers reside in each slave port of the crossbar switch Read and write transfers require two bus clock cycles The registers can only be read from and written to in supervisor mode Additionally these registers can only be read from...

Page 341: ...0xFC00_4310 Control Register Slave 3 XBS_CRS3 32 R W 0x0000_0000 15 4 2 15 5 0xFC00_4400 Priority Register Slave 4 XBS_PRS4 32 R W 0x6540_3210 15 4 1 15 4 0xFC00_4410 Control Register Slave 4 XBS_CRS4 32 R W 0x0000_0000 15 4 2 15 5 0xFC00_4500 Priority Register Slave 5 XBS_PRS5 32 R W 0x6540_3210 15 4 1 15 4 0xFC00_4510 Control Register Slave 5 XBS_CRS5 32 R W 0x0000_0000 15 4 2 15 5 0xFC00_4700 P...

Page 342: ... master has level 1 highest priority when accessing the slave port 001 This master has level 2 priority when accessing the slave port 010 This master has level 3 priority when accessing the slave port 011 This master has level 4 priority when accessing the slave port 100 This master has level 5 priority when accessing the slave port 101 This master has level 6 priority when accessing the slave por...

Page 343: ...e slave port 0 Fixed priority 1 Round robin rotating priority 7 6 Reserved must be cleared 5 4 PCTL Parking control Determines the slave port s parking control The low power park feature results in an overall power savings if the slave port is not saturated however this forces an extra latency clock when any master tries to access the slave port while not in use because it is not parked on any mas...

Page 344: ...burst transfer or locked transfer before it is granted control of the slave port If the new requesting master s priority level is lower than the master that currently has control of the slave port the new requesting master is forced to wait until the current master runs one of the following cycles An IDLE cycle A non IDLE cycle to a location other than the current slave port 15 5 1 2 Round Robin P...

Page 345: ...ters XBS_PRSn the crossbar switch responds with a bus error refer to Section 14 2 5 SCM Interrupt Status Register SCMISR and the registers are not updated 15 6 Initialization Application Information No initialization is required by or for the crossbar switch Hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state Settings and priorities sh...

Page 346: ...be used as general purpose digital I O GPIO pins In some cases the pin function is set by the operating mode and the alternate pin functions are not supported Each GPIO port has registers that configure monitor and control the port pins Figure 16 1 is a block diagram of the device ports The GPIO functionality of the port IRQ pins is selected by the edge port module They are shown in the figure onl...

Page 347: ...C0L0 Port DMA DACK1 ULPI_DIR PDMA3 DREQ1 USB_CLKIN PDMA2 DACK0 DSPI_PCS3 PDMA1 DREQ0 PDMA0 DSPI_SOUT SBF_DO PDSPI0 FEC1_MDC ATA_DIOR PFECI2C5 FEC1_MDIO ATA_DIOW PFECI2C4 FEC1_TXCLK FEC1_RMII_REF_CLK ATA_DATA11 PFEC1H7 FEC1_TXD 3 2 ATA_DATA 2 1 PFEC1L 7 6 Port FEC1H Port FEC1L FEC1_TXEN FEC1_RMII_TXEN ATA_DATA8 PFEC1H6 FEC1_TXD0 FEC1_RMII_TXD0 ATA_DATA9 PFEC1H5 FEC1_COL ATA_DATA7 PFEC1H4 FEC1_RXCLK...

Page 348: ...rpose I O support for all ports Registers for storing output pin data Registers for controlling pin data direction Registers for reading current pin state Registers for setting and clearing output pin data registers Control of functional pad drive strengths Slew rate control for PCI and SDRAM pins 16 2 External Signal Description The external pins controllable by this module are listed under the G...

Page 349: ...e FB_BE BWE 3 0 FB_BE BWE 3 0 FB_CS 3 1 FB_CS 3 1 FB_OE FB_OE FB_R W FB_R W FB_TA FB_TA FB_TS FB_TS PCI_GNT 3 0 GPIO PCI_GNT 3 0 PCI_REQ 3 0 GPIO PCI_REQ 3 0 IRQ1 GPIO PCI_INTA and configured as an agent ATA_RESET GPIO ATA reset Table 16 2 MCF5445x Signal Information and Muxing Signal Name GPIO Alternate 1 Alternate 2 Pull up U 1 Pull down D Direction 2 Voltage Domain MCF54450 MCF54451 256 MAPBGA ...

Page 350: ...A4 AB3 FB_CS0 O EVDD C4 Y4 FB_OE PFBCTL3 O EVDD A2 AA1 FB_R W PFBCTL2 O EVDD B2 AA3 FB_TA PFBCTL1 U I EVDD B1 AB2 FB_TS PFBCTL0 FB_ALE FB_TBST O EVDD A3 Y3 PCI Controller5 PCI_AD 31 0 FB_A 31 0 I O EVDD C11 D11 A10 B10 J4 G2 G3 F1 D12 C12 B12 A11 B11 B9 D9 D10 A8 B8 A5 B5 A4 A3 B3 D4 D3 E3 E1 F3 C2 D2 C1 FB_A 23 0 I O EVDD K14 13 J15 13 H13 15 G15 13 F14 13 E15 13 D16 B16 C15 B15 C14 D15 C16 D14 P...

Page 351: ...9 22 R20 22 N19 P20 21 SD_BA 1 0 O SDVDD P4 T5 P22 P19 SD_CAS O SDVDD T6 L19 SD_CKE O SDVDD N5 N22 SD_CLK O SDVDD T9 L22 SD_CLK O SDVDD T8 M22 SD_CS 1 0 O SDVDD P6 R6 L20 M20 SD_D 31 16 I O SDVDD N6 T7 N7 P7 R7 R8 P8 N8 N9 T10 R10 P10 N10 T11 R11 P11 L21 K22 K21 K20 J20 J19 J21 J22 H20 G22 G21 G20 G19 F22 F21 F20 SD_DM 3 2 O SDVDD P9 N12 H21 E21 SD_DQS 3 2 O SDVDD R9 N11 H22 E22 SD_RAS O SDVDD P5 ...

Page 352: ...FEC0_RXD0 PFEC0H1 FEC0_RMII_RXD0 I EVDD H2 AB10 FEC0_RXER PFEC0L0 FEC0_RMII_RXER I EVDD H3 AA10 FEC0_TXCLK PFEC0H7 FEC0_RMII_ REF_CLK I EVDD H4 Y10 FEC0_TXD 3 2 PFEC0L 7 6 ULPI_DATA 3 2 O EVDD J1 J2 W10 AB11 FEC0_TXD1 PFEC0L5 FEC0_RMII_TXD1 O EVDD J3 AA11 FEC0_TXD0 PFEC0H5 FEC0_RMII_TXD0 O EVDD J4 Y11 FEC0_TXEN PFEC0H6 FEC0_RMII_TXEN O EVDD K1 W11 FEC0_TXER PFEC0L4 ULPI_DATA0 O EVDD K2 AB12 FEC1 F...

Page 353: ...II_TXD0 ATA_DATA9 O EVDD Y20 FEC1_TXEN PFEC1H6 FEC1_RMII_TXEN ATA_DATA8 O EVDD AA21 FEC1_TXER PFEC1L4 ATA_DATA0 O EVDD AA22 USB On the Go USB_DM O USB VDD F16 A14 USB_DP O USB VDD E16 A15 USB_VBUS_EN PUSB1 USB_PULLUP ULPI_NXT O USB VDD E5 AA2 USB_VBUS_OC PUSB0 ULPI_STP UD7 I USB VDD B3 V4 ATA ATA_BUFFER_EN PATAH5 O EVDD Y13 ATA_CS 1 0 PATAH 4 3 O EVDD W21 W22 ATA_DA 2 0 PATAH 2 0 O EVDD V19 21 ATA...

Page 354: ...EVDD N16 B18 DSPI DSPI_PCS5 PCSS PDSPI6 O EVDD N14 D18 DSPI_PCS2 PDSPI5 O EVDD L13 A19 DSPI_PCS1 PDSPI4 SBF_CS O EVDD P14 B20 DSPI_PCS0 SS PDSPI3 U I O EVDD R16 D17 DSPI_SCK PDSPI2 SBF_CK I O EVDD R15 A20 DSPI_SIN PDSPI1 SBF_DI 8 I EVDD P15 B19 DSPI_SOUT PDSPI0 SBF_DO O EVDD N13 C20 UARTs U1CTS PUART7 I EVDD V3 U1RTS PUART6 O EVDD U4 U1RXD PUART5 I EVDD P3 U1TXD PUART4 O EVDD N3 U0CTS PUART3 I EVD...

Page 355: ...11 C21 PSTCLK TCLK I EVDD P13 C22 DSI TDI U I EVDD T15 C19 DSO TDO O EVDD T14 A21 BKPT TMS U I EVDD R14 B21 DSCLK TRST U I EVDD M13 B22 Test TEST D I EVDD M6 AB20 PLLTEST O EVDD K16 D15 Power Supplies IVDD E6 12 F5 F12 D6 D8 D14 F4 H4 N4 R4 W4 W7 W8 W12 W16 W19 EVDD G5 G12 H5 H12 J5 J12 K5 K12 L5 6 L12 D13 D19 G8 G11 G14 G16 J7 J16 L7 L16 N16 P7 R16 T8 T12 T14 T16 SD_VDD L7 11 M9 M10 F19 H19 K19 M...

Page 356: ... enable the GPIO mode on these pins 5 When the PCI is enabled all PCI bus pins come up configured as such This includes the PCI_GNT and PCI_REQ lines which have GPIO The IRQ1 PCI_INTA signal is a special case It comes up as PCI_INTA when booting as a PCI agent and as GPIO when booting as a PCI host For the 360 TEPBGA booting with PCI disabled results in all dedicated PCI pins being safe stated The...

Page 357: ..._4006 PODR_DMA 8 R W 0x0F 16 3 1 16 16 0xFC0A_4007 PODR_FECI2C 8 R W 0x3F 16 3 1 16 16 0xFC0A_4009 PODR_UART 8 R W 0xFF 16 3 1 16 16 0xFC0A_400A PODR_DSPI 8 R W 0x7F 16 3 1 16 16 0xFC0A_400B PODR_TIMER 8 R W 0x0F 16 3 1 16 16 0xFC0A_400C PODR_PCI 8 R W 0xFF 16 3 1 16 16 0xFC0A_400D PODR_USB 8 R W 0x03 16 3 1 16 16 0xFC0A_400E PODR_ATAH 8 R W 0x3F 16 3 1 16 16 0xFC0A_400F PODR_ATAL 8 R W 0x07 16 3 ...

Page 358: ...8 R W 0x00 16 3 2 16 18 0xFC0A_402C PDDR_FBADH 8 R W 0x00 16 3 2 16 18 0xFC0A_402D PDDR_FBADMH 8 R W 0x00 16 3 2 16 18 0xFC0A_402E PDDR_FBADML 8 R W 0x00 16 3 2 16 18 0xFC0A_402F PDDR_FBADL 8 R W 0x00 16 3 2 16 18 Port Pin Data Set Data Registers 0xFC0A_4030 PPDSDR_FEC0H 8 R W See Section 16 3 3 16 20 0xFC0A_4031 PPDSDR_FEC0L 8 R W See Section 16 3 3 16 20 0xFC0A_4032 PPDSDR_SSI 8 R W See Section ...

Page 359: ...SI 8 W 0x00 16 3 4 16 23 0xFC0A_404B PCLRR_FBCTL 8 W 0x00 16 3 4 16 23 0xFC0A_404C PCLRR_BE 8 W 0x00 16 3 4 16 23 0xFC0A_404D PCLRR_CS 8 W 0x00 16 3 4 16 23 0xFC0A_404E PCLRR_DMA 8 W 0x00 16 3 4 16 23 0xFC0A_404F PCLRR_FECI2C 8 W 0x00 16 3 4 16 23 0xFC0A_4051 PCLRR_UART 8 W 0x00 16 3 4 16 23 0xFC0A_4052 PCLRR_DSPI 8 W 0x00 16 3 4 16 23 0xFC0A_4053 PCLRR_TIMER 8 W 0x00 16 3 4 16 23 0xFC0A_4054 PCLR...

Page 360: ... R W See Section 16 3 5 13 16 36 0xFC0A_4072 PAR_PCI 16 R W See Section 16 3 5 14 16 36 Mode Select Control Registers 0xFC0A_4074 MSCR_SDRAM 8 R W 0xFF 16 3 6 16 38 0xFC0A_4075 MSCR_PCI 8 R W See Section 16 3 7 16 39 Drive Strength Control Registers 0xFC0A_4078 DSCR_I2C 8 R W 0x03 16 3 8 16 39 0xFC0A_4079 DSCR_FLEXBUS 8 R W 0xFF 16 3 8 16 39 0xFC0A_407A DSCR_FEC 8 R W 0x0F 16 3 8 16 39 0xFC0A_407B...

Page 361: ...rresponding bits in the PPDSDR_x register To clear bits in a PODR_x register clear the PODR_x bits or clear the corresponding bits in the PCLRR_x register 0xFC0A_4083 DSCR_USB 8 R W 0x03 16 3 8 16 39 0xFC0A_4084 DSCR_ATA 8 R W 0x03 16 3 8 16 39 Address 0xFC0A_4000 PODR_FEC0H 0xFC0A_4001 PODR_FEC0L 0xFC0A_4009 PODR_UART 0xFC0A_400C PODR_PCI 0xFC0A_4010 PODR_FEC1H 0xFC0A_4011 PODR_FEC1L 0xFC0A_4014 ...

Page 362: ...Data Registers PODR_SSI Address 0xFC0A_4003 PODR_FBCTL 0xFC0A_4004 PODR_BE 0xFC0A_4006 PODR_DMA 0xFC0A_400B PODR_TIMER Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 PODR_x W Reset 0 0 0 0 1 1 1 1 Figure 16 6 Port x Output Data Registers PODR_x Address 0xFC0A_400F PODR_ATAL Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 0 PODR_ATAL W Reset 0 0 0 0 0 1 1 1 Figure 16 7 Port ATAL Output Data Regi...

Page 363: ...an input Address 0xFC0A_400D PODR_USB Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 PODR_USB W Reset 0 0 0 0 0 0 1 1 Figure 16 9 Port USB Output Data Registers PODR_USB Table 16 5 PODR_x Field Descriptions Field Description PODR_x Port x output data bits 0 Drives 0 when the port x pin is general purpose output 1 Drives 1 when the port x pin is general purpose output Note See above figures f...

Page 364: ...rection Registers PDDR_x Address 0xFC0A_401A PDDR_SSI Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 PDDR_SSI W Reset 0 0 0 0 0 0 0 0 Figure 16 13 Port PWM Output Data Registers PDDR_SSI Address 0xFC0A_401B PDDR_FBCTL 0xFC0A_401C PDDR_BE 0xFC0A_401E PDDR_DMA 0xFC0A_4023 PDDR_TIMER Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 PDDR_x W Reset 0 0 0 0 0 0 0 0 Figure 16 14 Port x Output Data Regist...

Page 365: ...g a PPDSDR_x register returns the current state of the port x pins Setting a PPDSDR_x register sets the corresponding bits in the PODR_x register Writing zeroes has no effect Address 0xFC0A_401D PDDR_CS Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 PDDR_CS 0 W Reset 0 0 0 0 0 0 0 0 Figure 16 16 Port CS Output Data Registers PDDR_CS Address 0xFC0A_4025 PDDR_USB Access User read write 7 6 5 4 3 2...

Page 366: ...a Registers PPDSDR_x Address 0xFC0A_403A PPDSDR_DSPI Access User read write 7 6 5 4 3 2 1 0 R 0 PPDR_DSPI W PSDR_DSPI Reset 0 PDSPI6 PDSPI5 PDSPI4 PDSPI3 PDSPI2 PDSPI1 PDSPI0 Figure 16 19 Port DSPI Pin Data Set Data Registers PPDSDR_DSPI Address 0xFC0A_4037 PPDSDR_FECI2C 0xFC0A_403E PPDSDR_ATAH Access User read write 7 6 5 4 3 2 1 0 R 0 0 PPDR_x W PSDR_x Reset 0 0 Px5 Px4 Px3 Px2 Px1 Px0 Figure 16...

Page 367: ...Reset 0 0 0 0 0 PATAL2 PATAL1 PATAL0 Figure 16 23 Port ATAL Pin Data Set Data Registers PPDSDR_ATAL Address 0xFC0A_4035 PPDSDR_CS Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 PPDR_CS 0 W PSDR_CS Reset 0 0 0 0 PCS3 PCS2 PCS1 0 Figure 16 24 Port CS Pin Data Set Data Registers PPDSDR_CS Address 0xFC0A_403D PPDSDR_USB Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 PPDR_USB W PSDR_USB Reset 0...

Page 368: ...Note See above figures for bit field positions Address 0xFC0A_4048 PCLRR_FEC0H 0xFC0A_4049 PCLRR_FEC0L 0xFC0A_4051 PCLRR_UART 0xFC0A_4054 PCLRR_PCI 0xFC0A_4058 PCLRR_FEC1H 0xFC0A_4059 PCLRR_FEC1L 0xFC0A_405C PCLRR_FBADH 0xFC0A_405D PCLRR_FBADMH 0xFC0A_405E PCLRR_FBADML 0xFC0A_405F PCLRR_FBADL Access User write only 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W PCLRR_x Reset 0 0 0 0 0 0 0 0 Figure 16 26 Port...

Page 369: ...Registers PCLRR_SSI Address 0xFC0A_4046 PCLRR_FBCTL 0xFC0A_404C PCLRR_BE 0xFC0A_404E PCLRR_DMA 0xFC0A_4053 PCLRR_TIMER Access User write only 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W PCLRR_x Reset 0 0 0 0 0 0 0 0 Figure 16 30 Port x Clear Output Data Registers PCLRR_x Address 0xFC0A_4057 PCLRR_ATAL Access User write only 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 W PCLRR_ATAL Reset 0 0 0 0 0 0 0 0 Figure 16 31 Po...

Page 370: ...FEC0 and FEC1 pins Address 0xFC0A_4055 PCLRR_USB Access User write only 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W PCLRR_USB Reset 0 0 0 0 0 0 0 0 Figure 16 33 Port USB Clear Output Data Registers PCLRR_USB Table 16 8 PCLRR_x Field Descriptions Field Description PCLRR_x Port x clear data bits 0 Clears corresponding PODR_x bit 1 No effect Note See above figures for bit field positions Address 0xFC0A_4060 ...

Page 371: ...GPIO PAR_FEC1 Meaning 000 FEC1 pins configured for GPIO 001 FEC1 pins configured for ATA data functions 010 FEC1 pins configured for FEC RMII functions MII only pins are configured for ATA data functions 011 FEC1 pins configured for FEC RMII functions MII only pins are configured for GPIO 100 Reserved 101 Reserved 110 Reserved 111 FEC1 pins configured for FEC MII functions PAR_FEC0 Meaning 000 FEC...

Page 372: ...ed as ULPI data direction function 10 Reserved 11 DACK1 configured for DMA acknowledge 1 function 5 4 PAR_DREQ1 DREQ1 pin assignment Configures the DREQ1 pin for one of its primary functions or GPIO 00 DREQ1 configured as GPIO 01 DREQ1 configured as USB input clock function 10 Reserved 11 DREQ1 configured for DMA request 1 function 3 2 PAR_DACK0 DACK0 pin assignment Configures the DACK0 pin for on...

Page 373: ... enable function 11 FB_TS pin configured for FlexBus transfer start function 2 0 Reserved should be cleared Address 0xFC0A_4063 PAR_DSPI Access User read write 7 6 5 4 3 2 1 0 R 0 PAR_PCS5 PAR_PCS2 PAR_PCS1 PAR_PCS0 PAR_SIN PAR_SOUT PAR_SCK W Reset 0 0 0 0 0 0 0 0 Figure 16 37 DSPI Pin Assignment Register PAR_DSPI Table 16 12 PAR_DSPI Field Descriptions Field Description 7 Reserved should be clear...

Page 374: ...2 PAR_BE1 PAR_BE0 W Reset 1 1 1 1 0 1 0 1 Figure 16 38 Byte Enable Pin Assignment Register PAR_BE Table 16 13 PAR_BE Field Descriptions Field Description 7 6 PAR_BE3 FB_BE3 pin assignment 00 FB_BE3 pin configured for GPIO 01 Reserved 10 FB_BE3 pin configured for FlexBus transfer size 1 function 11 FB_BE3 pin configured for FlexBus byte enable 3 function 5 4 PAR_BE2 FB_BE2 pin assignment 00 FB_BE2 ...

Page 375: ...re 16 39 Chip Select Pin Assignment Register PAR_CS Table 16 14 PAR_CS Field Descriptions Field Description 7 4 Reserved should be cleared 3 PAR_CS3 FB_CS3 pin assignment 0 FB_CS3 pin configured for GPIO 1 FB_CS3 pin configured for FlexBus chip select 3 function 2 PAR_CS2 FB_CS2 pin assignment 0 FB_CS2 pin configured for GPIO 1 FB_CS2 pin configured for FlexBus chip select 2 function 1 PAR_CS1 FB_...

Page 376: ...A_4067 PAR_USB Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 PAR_VBUSEN PAR_VBUSOC W Reset 0 0 0 0 0 0 0 0 Figure 16 41 USB Pin Assignment PAR_USB Table 16 16 PAR_USB Field Descriptions Field Description 7 4 Reserved should be cleared 3 2 PAR_VBUSEN 1 0 PAR_VBUSOC USB VBUS pin assignment Configure the USB VBUS pins for one of their primary functions or GPIO PAR_T3IN PAR_T2IN PAR_T1IN PAR_T0IN 0...

Page 377: ...TS pin configured for GPIO 1 U1RTS pin configured for UART1 request to send function 5 PAR_U1RXD U1RXD pin assignment 0 U1RXD pin configured for GPIO 1 U1RXD pin configured for UART1 receive data function 4 PAR_U1TXD U1TXD pin assignment 0 U1TXD pin configured for GPIO 1 U1TXD pin configured for UART1 transmit data function 3 PAR_U0CTS U0CTS pin assignment 0 U0CTS pin configured for GPIO 1 U0CTS p...

Page 378: ...d MDC pin assignment These bit fields configure the FEC1_MDC and FEC1_MDIO pins for one of their primary functions or GPIO 7 Reserved should be cleared 6 PAR_MDC0 FEC0 MDC pin assignment 0 FEC0_MDC pin configured for GPIO 1 FEC0_MDC pin configured for FEC0 management data clock function 5 Reserved should be cleared 4 PAR_MDIO0 FEC0 MDIO pin assignment 0 FEC0_MDIO pin configured for GPIO 1 FEC0_MDI...

Page 379: ... PAR_BCLK 7 6 PAR_FS 5 4 PAR_RXD 3 2 PAR_TXD SSI pin assignment Configure the SSI pins for one of their primary functions or GPIO 1 Reserved should be cleared 0 PAR_MCLK SSI_MCLK pin assignment 0 SSI_MCLK pin configured for GPIO function 1 SSI_MCLK pin configured for SSI oversampling clock function Address 0xFC0A_406E PAR_ATA Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0...

Page 380: ...AR_DA2 ATA_DA2 pin assignment 0 ATA_DA2 pin configured as GPIO 1 ATA_DA2 pin configured for ATA address 2 function 6 PAR_DA1 ATA_DA1 pin assignment 0 ATA_DA1 pin configured as GPIO 1 ATA_DA1 pin configured for ATA address 1 function 5 PAR_DA0 ATA_DA0 pin assignment 0 ATA_DA0 pin configured as GPIO 1 ATA_DA0 pin configured for ATA address 0 function 4 3 Reserved should be cleared 2 PAR_ARESET ATA_R...

Page 381: ...oot bit 103 Figure 16 46 IRQ Pin Assignment PAR_IRQ Table 16 21 PAR_IRQ Field Descriptions Field Description 7 5 Reserved should be cleared 4 PAR_IRQ4 IRQ4 pin assignment 0 IRQ4 pin configured as GPIO or external interrupt request 4 function as determined by the edge port module See Chapter 18 Edge Port Module EPORT for details 1 IRQ4 pin configured for SSI input clock fuction 3 2 Reserved should ...

Page 382: ...nt Configure the PCI_GNT0 pin for one of its primary functions or GPIO 0 PCI_GNT0 pin configured for GPIO 1 PCI_GNT0 pin configured for PCI grant 0 function 7 6 PAR_REQ3 PCI_REQ3 assignment Configure the PCI_REQ3 pin for one of its primary functions or GPIO 00 PCI_REQ3 pin configured for GPIO 01 Reserved 10 PCI_REQ3 pin configured for ATA interrupt request function 11 PCI_REQ3 pin configured for P...

Page 383: ...obile DDR 01 Full strength 1 8V mobile DDR 10 1 8V DDR2 without on chip termination 11 2 5V DDR1 5 4 MSCR_ SDDQS SD_DQS 3 2 slew rate mode Controls the strength of the SDRAM DQS pins 00 Half strength 1 8V mobile DDR 01 Full strength 1 8V mobile DDR 10 1 8V DDR2 without on chip termination 11 2 5V DDR1 3 2 MSCR_ SDCLK SD_CLK and SD_CLK slew rate mode Controls the strength of the SDRAM clock pins 00...

Page 384: ...re read write NOTE These drive strength settings are effective in all non JTAG modes regardless of the current functions of the pins Address 0xFC0A_4075 MSCR_PCI Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 MSCR_PCI W Reset 0 0 0 0 0 0 0 See Note Note Reset state is 1 when BOOTMOD 1 0 equals 00 the value of FB_AD 2 when BOOTMOD 1 0 equals 10 or the value of serial boot bit 104 when BOOTM...

Page 385: ...gth Control Registers DSCR_x Address 0xFC0A_407A DSCR_FEC Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 DSE_FEC1 DSE_FEC0 W Reset 0 0 0 0 1 1 1 1 Figure 16 51 FEC Drive Strength Control Register DSCR_FEC Address 0xFC0A_407B DSCR_UART Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 DSE_UART1 DSE_UART0 W Reset 0 0 0 0 1 1 1 1 Figure 16 52 UART Drive Strength Control Register DSCR_UART Address 0x...

Page 386: ...r individual bit fields DSE_FEC1 FEC1_MDC FEC1_MDIO FEC1_COL FEC1_CRS FEC1_RXCLK FEC1_RXDV FEC1_RXER FEC1_RXD 3 0 FEC1_TXCLK FEC1_TXD 3 0 FEC1_TXEN and FEC1_TXER DSE_FEC0 FEC0_MDC FEC0_MDIO FEC0_COL FEC0_CRS FEC0_RXCLK FEC0_RXDV FEC0_RXER FEC0_RXD 3 0 FEC0_TXCLK FEC0_TXD 3 0 FEC0_TXEN and FEC0_TXER DSCR_UART See below for individual bit fields DSE_UART1 U1RXD U1TXD U1CTS and U1RTS DSE_UART0 U0RXD ...

Page 387: ...ins configured as outputs Reading a PODR_x register returns the current state of the register regardless of the state of the corresponding pins Reading a PPDSDR_x register returns the current state of the corresponding pins when configured as general purpose I O regardless of whether the pins are inputs or outputs Every GPIO port has a PPDSDR_x register and a clear register PCLRR_x for setting or ...

Page 388: ...g 16 5 Initialization Application Information The initialization for this module is done during reset configuration All registers are reset to a predetermined state Refer to Section 16 3 Memory Map Register Definition for more details on reset and initialization FB_CLK Output Data Output Pin Register ...

Page 389: ...Pin Multiplexing and Control 16 44 Freescale Semiconductor ...

Page 390: ...ate The interrupt architecture of ColdFire is exactly the same as the M68000 family where there is a 3 bit encoded interrupt priority level sent from the interrupt controller to the core providing 7 levels of interrupt requests Level 7 represents the highest priority interrupt level while level 1 is the lowest priority The processor samples for active interrupt requests once per instruction by com...

Page 391: ...evious 68K ColdFire cores In this approach all IACK cycles are directly managed by the interrupt controller so the requesting peripheral device is not accessed during the IACK As a result the interrupt request must be explicitly cleared in the peripheral during the interrupt service routine For more information see Section 17 3 1 3 Interrupt Vector Determination ColdFire processors guarantee that ...

Page 392: ...K 8 R W 0x0F 17 2 8 17 10 0xFC04_8040 n n 0 63 Interrupt Control Registers ICR0n 8 R W 0x00 17 2 9 17 11 0xFC04_80E0 Software Interrupt Acknowledge SWIACK0 8 R 0x00 17 2 10 17 15 0xFC04_80E0 4n n 1 7 Level n Interrupt Acknowledge Registers LnIACK0 8 R 0x18 17 2 10 17 15 Interrupt Controller 1 0xFC04_C000 Interrupt Pending Register High IPRH1 32 R 0x0000_0000 17 2 1 17 4 0xFC04_C004 Interrupt Pendi...

Page 393: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17 1 Interrupt Pending Register High IPRHn Table 17 3 IPRHn Field Descriptions Field Description 31 0 INT Interrupt pending Each bit corresponds to an interrupt source The corresponding IMRHn bit determines whether an interrupt condition can generate an interrupt At every system clock the IPRHn samples the signal generated by the...

Page 394: ...rite a higher level interrupt mask to the status register before setting the mask in the IMR or the module s interrupt mask register After the mask is set return the interrupt mask in the status register to its previous value Because level 7 interrupts cannot be disabled in the status register prior to masking use of the IMR or module interrupt mask registers to disable level 7 interrupts is not r...

Page 395: ... The corresponding IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is set 0 The corresponding interrupt source is not masked 1 The corresponding interrupt source is masked Address 0xFC04_800C IMRL0 0xFC04_C00C IMRL1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R INT_MASK W Reset 1 1 1 1 1 1 1 1...

Page 396: ...pt on the corresponding source Address 0xFC04_8014 INTFRCL0 0xFC04_C014 INTFRCL1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R INTFRCL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17 6 Interrupt Force Register Low INTFRCLn Table 17 8 INTFRCLn Field Descriptions Field Description 31 0 INTFRCL Interrup...

Page 397: ...l n request does not affect the processor s bus master priority 8 6 Reserved must be cleared 5 EMASK If set the interrupt controller automatically loads the level of an interrupt request into the CLMASK current level mask when the acknowledge is performed At the exact same cycle the value of the current interrupt level mask is saved in the SLMASK saved level mask register This feature can be used ...

Page 398: ... the physical request source and the CLMASK register is loaded with the level number associated with the request After the CLMASK register is updated then all interrupt requests with level numbers equal to or less than this value are masked by the controller and are not allowed to cause the assertion of the interrupt signal to the processor core As the CLMASK register is updated during the IACK cy...

Page 399: ...e read the former value is saved in the SLMASK register Typically after a level n interrupt request is managed the service routine restores the saved level mask value into the current level mask register to re enable the lower priority requests NOTE Only one copy of this register exists among the two interrupt controller modules All reads and writes to this register must be made to the INTC0 memor...

Page 400: ...rocessor Address 0xFC04_801F SLMASK Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 SLMASK W Reset 0 0 0 0 1 1 1 1 Figure 17 11 Saved Level Mask Register SLMASK Table 17 13 SLMASK Field Descriptions Field Description 7 4 Reserved must be cleared 3 0 SLMASK Saved level mask Defines the saved level mask See the CLMASK field definition for more information on the specific values Address 0xFC04_8040 ...

Page 401: ... CINT 4 13 EDMA_INTR INT05 DMA Channel 5 transfer complete Write EDMA_CINTR CINT 5 14 EDMA_INTR INT06 DMA Channel 6 transfer complete Write EDMA_CINTR CINT 6 15 EDMA_INTR INT07 DMA Channel 7 transfer complete Write EDMA_CINTR CINT 7 16 EDMA_INTR INT08 DMA Channel 8 transfer complete Write EDMA_CINTR CINT 8 17 EDMA_INTR INT09 DMA Channel 9 transfer complete Write EDMA_CINTR CINT 9 18 EDMA_INTR INT1...

Page 402: ...R0 LC Late collision Write EIR0 LC 1 44 EIR0 HBERR Heartbeat error Write EIR0 HBERR 1 45 EIR0 GRA Graceful stop complete Write EIR0 GRA 1 46 EIR0 EBERR Ethernet bus error Write EIR0 EBERR 1 47 EIR0 BABT Babbling transmit error Write EIR0 BABT 1 48 EIR0 BABR Babbling receive error Write EIR0 BABR 1 49 FEC1 EIR1 TXF Transmit frame interrupt Write EIR1 TXF 1 50 EIR1 TXB Transmit buffer interrupt Writ...

Page 403: ...IFO underflow interrupt Write 1 to either RFOF or TFUF 40 RNG EI RNG interrupt flag Write RNGCR CI 1 41 42 Not Used 43 PIT0 PCSR0 PIF PIT interrupt flag Write PIF 1 or write PMR 44 PIT1 PCSR1 PIF PIT interrupt flag Write PIF 1 or write PMR 45 PIT2 PCSR2 PIF PIT interrupt flag Write PIF 1 or write PMR 46 PIT3 PCSR3 PIF PIT interrupt flag Write PIF 1 or write PMR 47 USB OTG USB_STS USB OTG interrupt...

Page 404: ...ed In general the software IACK is performed near the end of an interrupt service routine and if there are additional active interrupt sources the current interrupt service routine ISR passes control to the appropriate service routine but without taking another interrupt exception When the interrupt controller receives a software IACK read it returns the vector number associated with the highest u...

Page 405: ...and the interrupt mask register IMRn to determine if there are active requests This is the recognition phase The interrupt force register INTFRCn also factors into the generation of an active request 17 3 1 2 Interrupt Prioritization As an active request is detected it is translated into the programmed interrupt level Next the appropriate level masking is performed if this feature is enabled The l...

Page 406: ... bit position within the source to the actual interrupt vector number If there is no active interrupt source for the given level a special spurious interrupt vector vector_number equals 24 is returned and it is the responsibility of the service routine to manage this error situation This protocol implies the interrupting peripheral is not accessed during the acknowledge cycle because the interrupt...

Page 407: ...tus PST encoding Issuing the STOP instruction when the WCR ENBWCR bit is set causes the SCM to enter the mode specified in LPCR LPMD 3 The entry into a low power mode is processed by the low power mode control logic and the appropriate clocks usually those related to the high speed processor core are disabled 4 After entering the low power mode the interrupt controller enables a combinational logi...

Page 408: ... the appropriate vector number As the interrupt acknowledge read performs the vector number returns to the core The contents of the CLMASK register load into the SLMASK register and the CLMASK register updates to the level of the acknowledge interrupt Additionally the processor raises the interrupt mask in the status register SR I to match the level of the acknowledged request At the end of the co...

Page 409: ...le to access the interrupt controller with a software IACK to see if there are any pending properly enabled requests Checking for any pending interrupt requests at this time provides ability to initiate processing of another interrupt without the need to return from the original and incur the overhead of another interrupt exception At the conclusion of segment G the processor core returns to the o...

Page 410: ... NOTE Not all EPORT signals may be output from the device See Chapter 2 Signal Descriptions to determine which signals are available Figure 18 1 EPORT Block Diagram NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins refer to Chapter 16 Pin Multiplexing and Control prior to configuring the edge port module Internal Bus Synchronizer EPFRn EPPAR 2n 2n 1 ...

Page 411: ...sed for the level detect logic because no clocks are available 18 3 Signal Descriptions All EPORT pins default to general purpose input pins at reset The pin value is synchronized to the rising edge of FB_CLK when read from the EPORT pin data register EPPDR The values used in the edge level detect logic are also synchronized to the rising edge of FB_CLK These pins use Schmitt triggered input buffe...

Page 412: ...t and result in a bus error 0xFC09_4000 EPORT Pin Assignment Register EPPAR 16 R W 0x0000 18 4 1 18 3 0xFC09_4002 EPORT Data Direction Register EPDDR 8 R W 0x00 18 4 2 18 4 0xFC09_4003 EPORT Interrupt Enable Register EPIER 8 R W 0x00 18 4 3 18 5 Supervisor User Access Registers 0xFC09_4004 EPORT Data Register EPDR 8 R W 0xFF 18 4 4 18 5 0xFC09_4005 EPORT Pin Data Register EPPDR 8 R See Section 18 ...

Page 413: ... of its configuration as input or output Interrupt requests generated in the EPORT module can be masked by the interrupt controller module EPPAR functionality is independent of the selected pin direction Reset clears the EPPAn fields 00 Pin IRQn level sensitive 01 Pin IRQn rising edge triggered 10 Pin IRQn falling edge triggered 11 Pin IRQn falling edge and rising edge triggered Address 0xFC09_400...

Page 414: ... bit in EPIER is set EPORT generates an interrupt request when The corresponding bit in the EPORT flag register EPFR is set or later becomes set The corresponding pin level is low and the pin is configured for level sensitive operation Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin Reset clears EPIE7 EPIE0 0 Interrupt requests from corresponding EPORT pin di...

Page 415: ...not affect EPPDR Address 0xFC09_4006 EPFR Access User read write 7 6 5 4 3 2 1 0 R EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPF0 W w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 Figure 18 7 EPORT Port Flag Register EPFR Table 18 8 EPFR Field Descriptions Field Description 7 0 EPFn Edge port flag bits When an EPORT pin is configured for edge triggering its corresponding read write bit in EPFR indi...

Page 416: ...ce and destination address calculations and the actual data movement operations along with local memory containing transfer control descriptors for each channel 19 1 1 Block Diagram Figure 19 1 is a block diagram of the eDMA module Figure 19 1 eDMA Block Diagram 2 1 15 Transfer Control Descriptor TCD eDMA Engine Data Path eDMA eDMA Peripheral 0 Program Model Write Address Write Data Read Data Read...

Page 417: ...uter data transfer loop defined by a major iteration count Channel activation via one of three methods Explicit software initiation Initiation via a channel to channel linking mechanism for continual transfers Peripheral paced hardware requests one per channel Support for fixed priority and round robin channel arbitration Channel completion reported via optional interrupt requests One interrupt pe...

Page 418: ...ignal must negate after the DACKn assertion and on or before the second cycle following the data phase of the last internal bus write see Figure 19 2 If another service request is needed DREQn may simply remain asserted To request continuous service DREQn may remain continuously asserted Figure 19 2 DREQn and DACKn Timing After a service request has been initiated it cannot be canceled Removing a ...

Page 419: ...t regard to priority Table 19 2 eDMA Controller Memory Map Address Register Width bits Access Reset Value Section Page 0xFC04_4000 eDMA Control Register EDMA_CR 32 R W 0x0000_0000 19 4 1 19 4 0xFC04_4004 eDMA Error Status Register EDMA_ES 32 R 0x0000_0000 19 4 2 19 5 0xFC04_400E eDMA Enable Request Register EDMA_ERQ 16 R W 0x0000 19 4 3 19 8 0xFC04_4016 eDMA Enable Error Interrupt Register EDMA_EE...

Page 420: ...p byte count must be a multiple of the source and destination transfer sizes All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively Address 0xFC04_4000 EDMA_CR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ...

Page 421: ... bus error occurs the channel terminates after the read or write transaction which is already pipelined after errant access has completed If a bus error occurs on the last read prior to beginning the write sequence the write executes using the data captured during the bus error If a bus error occurs on the last write prior to switching to the next read sequence the read sequence executes before th...

Page 422: ...n address configuration error 1 The last recorded error was a configuration error detected in the TCDn_DADDR field TCDn_DADDR is inconsistent with TCDn_ATTR DSIZE 4 DOE Destination offset error 0 No destination offset configuration error 1 The last recorded error was a configuration error detected in the TCDn_DOFF field TCDn_DOFF is inconsistent with TCDn_ATTR DSIZE 3 NCE NBYTES CITER configuratio...

Page 423: ...The assignments between the DMA requests from the peripherals to the channels of the eDMA are shown in Table 19 6 Address 0xFC04_400E EDMA_ERQ Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ERQ 15 ERQ 14 ERQ 13 ERQ 12 ERQ 11 ERQ 10 ERQ 9 ERQ 8 ERQ 7 ERQ 6 ERQ 5 ERQ 4 ERQ 3 ERQ 2 ERQ 1 ERQ 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 5 eDMA Enable Request Register EDMA_ERQ Ta...

Page 424: ...egister The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller 10 DTER2 CAP or DTER2 REF SSISR TFE0 Timer 2 SSI0 Transmit1 11 DTER3 CAP or DTER3 REF SSISR TFE1 Timer 3 SSI1 Transmit1 12 DSPI_SR RFDF DSPI Receive 13 DSPI_SR TFFF DSPI Transmit 14 ATA_ISR DMA ATA Receive 15 ATA_ISR DMA ...

Page 425: ...er write causes the corresponding bit in the EDMA_ERQ to be cleared Setting the CAER bit provides a global clear function forcing the entire contents of the EDMA_ERQ to be cleared disabling all DMA request inputs Reads of this register return all zeroes Address 0xFC04_4018 EDMA_SERQ Access User write only 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W SAER SERQ Reset 0 0 0 0 0 0 0 0 Figure 19 7 eDMA Set Enab...

Page 426: ...leared Setting the CAEE bit provides a global clear function forcing the EDMA_EEI contents to be cleared disabling all DMA request inputs Reads of this register return all zeroes Table 19 9 EDMA_CERQ Field Descriptions Field Description 7 Reserved must be cleared 6 CAER Clear all enable requests 0 Clear only those EDMA_ERQ bits specified in the CERQ field 1 Clear all bits in EDMA_ERQ 5 4 Reserved ...

Page 427: ... 0 0 0 0 0 0 0 W CAEE CEEI Reset 0 0 0 0 0 0 0 0 Figure 19 10 eDMA Clear Enable Error Interrupt Register EDMA_CEEI Table 19 11 EDMA_CEEI Field Descriptions Field Description 7 Reserved must be cleared 6 CAEE Clear all enable error interrupts 0 Clear only those EDMA_EEI bits specified in the CEEI field 1 Clear all bits in EDMA_EEI 5 4 Reserved must be cleared 3 0 CEEI Clear enable error interrupt C...

Page 428: ... data value on a register write causes the START bit in the corresponding transfer control descriptor to be set Setting the SAST bit provides a global set function forcing all START bits to be set Reads of this register return all zeroes 5 4 Reserved must be cleared 3 0 CINT Clear interrupt request Clears the corresponding bit in EDMA_INT Address 0xFC04_401D EDMA_CERR Access User write only 7 6 5 ...

Page 429: ...ter EDMA_SSRT Table 19 14 EDMA_SSRT Field Descriptions Field Description 7 Reserved must be cleared 6 SAST Set all START bits activates all channels 0 Set only those TCDn_CSR START bits specified in the SSRT field 1 Set all bits in TCDn_CSR START 5 4 Reserved must be cleared 3 0 SSRT Set START bit Sets the corresponding bit in TCDn_CSR START Address 0xFC04_401F EDMA_CDNE Access User write only 7 6...

Page 430: ... outputs of this register are enabled by the contents of the EDMA_EEI and then routed to the interrupt controller During the execution of the interrupt service routine associated with any DMA errors it is software s responsibility to clear the appropriate bit negating the error interrupt request Typically a write to the EDMA_CERR in the interrupt service routine is used for this purpose The normal...

Page 431: ...it is again eligible for preemption If any higher priority channel is requesting service the restored channel is suspended and the higher priority channel is serviced Nested preemption attempting to preempt a preempting channel is not supported After a preempting channel begins execution it cannot be preempted Preemption is available only when fixed arbitration is selected Address 0xFC04_402E EDMA...

Page 432: ...ty Channel priority when fixed priority arbitration is enabled Table 19 19 TCDn Memory Structure eDMA Offset TCDn Register Name Abbreviation Width bits 0xFC04_5000 0x20 n Source Address TCDn_SADDR 32 0xFC04_5004 0x20 n Transfer Attributes TCDn_ATTR 16 0xFC04_5006 0x20 n Signed Source Address Offset TCDn_SOFF 16 0xFC04_5008 0x20 n Minor Byte Count TCDn_NBYTES 32 0xFC04_500C 0x20 n Last Source Addre...

Page 433: ...ues requiring power of 2 size bytes the queue should start at a 0 modulo size address and the SMOD field should be set to the appropriate value for the queue freezing the desired number of upper address bits The value programmed into this field specifies the number of lower address bits allowed to change For a circular queue application the SOFF is typically set to the transfer size to implement p...

Page 434: ...ng the bandwidth control field or via preemption After the minor count is exhausted the SADDR and DADDR values are written back into the TCD memory the major iteration count is decremented and restored to the TCD memory If the major iteration count is completed additional processing is performed Note An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer Address 0xFC04_500C 0x20 n TCDn_S...

Page 435: ...isabled 1 The channel to channel linking is enabled Note This bit must be equal to the BITER E_LINK bit Otherwise a configuration error is reported 14 13 Reserved must be cleared 12 9 LINKCH Link channel number If channel to channel linking is enabled E_LINK 1 then after the minor loop is exhausted the eDMA engine initiates a channel service request to the channel defined by these four bits by set...

Page 436: ...escription 31 0 DLAST_SGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel scatter gather If TCDn_CSR E_SG 0 then Adjustment value added to the destination address at the completion of the major iteration count This value can apply to restore the destination address to the initial value or adjust the address to refere...

Page 437: ...hausted the eDMA engine initiates a channel service request at the channel defined by these four bits by setting that channel s TCDn_CSR START bit 0 15 Link to DMA channel 0 15 Note When the software loads the TCD this field must be set equal to the corresponding CITER field Otherwise a configuration error is reported As the major iteration count is exhausted the contents of this field is reloaded...

Page 438: ...active This flag signals the channel is currently in execution It is set when channel service begins and the eDMA clears it as the minor loop completes or if any error condition is detected 5 MAJOR_E_LINK Enable channel to channel linking on major loop complete As the channel completes the major loop this flag enables the linking to another channel defined by MAJOR_LINKCH The link target channel i...

Page 439: ... values for the TCDn_ SADDR DADDR CITER back to local memory If the major iteration count is exhausted additional processing are performed including the final address pointer updates reloading the TCDn_CITER field and a possible fetch of the next TCDn from memory as part of a scatter gather operation 2 INT_HALF Enable an interrupt when major counter is half complete If this flag is set the channel...

Page 440: ...ion is 32 bit data two reads are performed then one 32 bit write Transfer Control Descriptor Memory Memory Controller This logic implements the required dual ported controller managing accesses from the eDMA engine as well as references from the internal peripheral bus As noted earlier in the event of simultaneous accesses the eDMA engine is given priority and the peripheral transaction is stalled...

Page 441: ... The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write This source read destination write processing continues until the minor byte count has transferred 2 1 n 1 Transfer Control Descriptor TCD eDMA Engine Data Path eDMA eDMA Peripheral 0 Program Model Write Address Write Data Read Data ...

Page 442: ...dress adjustments and reloading of the BITER field into the CITER Assertion of an optional interrupt request also occurs at this time as does a possible fetch of a new TCD from memory using the scatter gather address pointer included in the descriptor The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 19 31 2 1 n 1 Transfer Control Descriptor TCD eDMA Engin...

Page 443: ...efault is desired 3 Enable error interrupts in the EDMA_EEI if so desired 4 Write the 32 byte TCD for each channel that may request service 5 Enable any hardware service requests via the EDMA_ERQ 6 Request channel service by software setting the TCDn_CSR START bit or hardware slave device asserting its eDMA peripheral request signal 2 1 n 1 Transfer Control Descriptor TCD eDMA Engine Data Path eDM...

Page 444: ...xecutes interrupts major loop channel linking and scatter gather operations if enabled Table 19 32 shows how each DMA request initiates one minor loop transfer iteration without CPU intervention DMA arbitration can occur after each minor loop and one level of minor loop DMA preemption is allowed The number of minor loops in a major loop is specified by the beginning iteration count BITER Table 19 ...

Page 445: ...ductor Table 19 33 lists the memory array terms and how the TCD settings interrelate Table 19 32 Example of Multiple Loop Iterations Current Major Loop Iteration Count CITER DMA Request Minor Loop Major Loop 3 DMA Request Minor Loop 2 DMA Request Minor Loop 1 ...

Page 446: ...channel with that priority is selected by arbitration and executed by the eDMA engine The hardware service request handshake signals error interrupts and error reporting is associated with the selected channel 19 6 3 DMA Arbitration Mode Considerations 19 6 3 1 Fixed Channel Arbitration In this mode the channel service request from the highest priority channel is selected to execute Table 19 33 Me...

Page 447: ...on memory has a longword wide port located at 0x2000 The address offsets are programmed in increments to match the transfer size one byte for the source and four bytes for the destination The final source and destination addresses are adjusted to return to their beginning values Example 19 1 Single Request DMA Transfer TCDn_CITER TCDn_BITER 1 TCDn_NBYTES 16 TCDn_SADDR 0x1000 TCDn_SOFF 1 TCDn_ATTR ...

Page 448: ...e same as previous The only fields that change are the major loop iteration count and the final address offsets The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration After the channel s hardware requests are enabled in EDMA_ERQ the slave device initiates channel service requests TCDn_CITER TCDn_BITER 2 TCDn_SLAST 32 TCDn_DLAST_SGA 32 This would generate th...

Page 449: ...te longword to location 0x2014 second iteration of the minor loop e Read byte from location 0x1018 read byte from location 0x1019 read byte from 0x101A read byte from 0x101B f Write longword to location 0x2018 third iteration of the minor loop g Read byte from location 0x101C read byte from location 0x101D read byte from 0x101E read byte from 0x101F h Write longword to location 0x201C last iterati...

Page 450: ...s set Polling the TCDn_CSR ACTIVE bit may be inconclusive because the active status may be missed if the channel execution is short in duration The TCD status bits execute the following sequence for a software activated channel The best method to test for minor loop completion when using hardware peripheral initiated service requests is to read the TCDn_CITER field and test for a change The hardwa...

Page 451: ...ative priority outstanding requests become undefined Channel priorities are treated as equal constantly rotating when round robin arbitration mode is selected The TCDn_CSR ACTIVE bit for the preempted channel remains asserted throughout the preemption The preempted channel is temporarily suspended while the preempting channel executes one major loop iteration If two TCDn_CSR ACTIVE bits are set si...

Page 452: ...ITER E_LINK bit and the TCDn_BITER E_LINK bit must equal or a configuration error is reported The CITER and BITER vector widths must be equal to calculate the major loop half way done interrupt point Table 19 35 summarizes how a DMA channel can link to another DMA channel i e use another channel s TCD at the end of a loop 19 6 7 Dynamic Programming This section provides recommended methods to chan...

Page 453: ...xecuting a dynamic channel link or dynamic scatter gather request 1 Set the TCDn_CSR MAJOR_E_LINK bit 2 Read back the TCDn_CSR MAJOR_E_LINK bit 3 Test the TCDn_CSR MAJOR_E_LINK request status a If the bit is set the dynamic link attempt was successful b If the bit is cleared the attempted dynamic link did not succeed the channel was already retiring This same coherency model is true for dynamic sc...

Page 454: ...an be directly connected to the following asynchronous or synchronous devices with little or no additional circuitry External boot ROMs Flash memories Programmable logic devices Other simple target slave devices For asynchronous devices a simple chip select based interface can be used The FlexBus interface has up to six general purpose chip selects FB_CS 5 0 The actual number of chip selects avail...

Page 455: ...ations Multiplexed 32 bit address and 32 bit data Multiplexed 32 bit address and 16 bit data non multiplexed 16 bit address and 16 bit data Multiplexed 32 bit address and 8 bit data non multiplexed 24 bit address and 8 bit data Non multiplexed 32 bit address with 32 bit data Table 20 1 FlexBus Signal Summary Signal Name I O1 Description FB_A 31 0 O In a non multiplexed configuration Address bus In...

Page 456: ...0 2 2 Chip Selects FB_CS 5 0 The chip select signal indicates which device is selected A particular chip select asserts when the transfer address is within the device s address space as defined in the base and mask address registers The actual number of chip selects available depends upon the pin configuration 20 2 3 Byte Enables Byte Write Enables FB_BE BWE 3 0 When driven low the byte enable FB_...

Page 457: ...he current bus operation The interface supports byte word and longword operand transfers and allows accesses to 8 16 and 32 bit data ports For misaligned transfers FB_TSIZ 1 0 indicates the size of each transfer For example if a longword access through a 32 bit port device occurs at a misaligned offset of 0x1 a byte is transferred first FB_TSIZ 1 0 01 a word is transferred next at offset 0x2 FB_TS...

Page 458: ...specified number of wait states or the external device may assert external FB_TA before the wait state countdown terminating the cycle early The device negates FB_CSn one cycle after the last FB_TA asserts During read cycles the peripheral must continue to drive data until FB_TA is recognized For write cycles the processor continues driving data one clock after FB_CSn is negated The number of wait...

Page 459: ...6 0xFC00_8004 n 0xC Chip Select Mask Register CSMRn n 0 5 32 R W 0x0000_0000 20 3 2 20 7 0xFC00_8008 n 0xC Chip Select Control Register CSCRn n 0 5 32 R W See Section 20 3 3 20 7 Address 0xFC00_8000 CSAR0 0xFC00_800C CSAR1 0xFC00_8018 CSAR2 0xFC00_8024 CSAR3 0xFC00_8030 CSAR4 0xFC00_803C CSAR5 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 460: ... bit is a don t care in chip select decode The block size for FB_CSn is 2n n number of bits set in respective CSMR BAM 16 For example if CSAR0 equals 0x0000 and CSMR0 BAM equals 0x0008 FB_CS0 addresses two discontinuous 64 KB memory blocks one from 0x0_0000 0x0_FFFF and one from 0x8_0000 0x8_FFFF Likewise for FB_CS0 to access 32 MB of address space starting at location 0x00_0000 FB_CS1 must begin ...

Page 461: ...s The number of wait states inserted before an internal transfer acknowledge is generated for a burst transfer except for the first termination which is controlled by the wait state count The secondary wait state is used only if the SWSEN bit is set Otherwise the WS value is used for all burst transfers 25 24 Reserved must be cleared 23 SWSEN Secondary wait state enable 0 The WS value inserts wait...

Page 462: ... states inserted after FB_CSn asserts and before an internal transfer acknowledge is generated WS 0 inserts zero wait states WS 0x3F inserts 63 wait states If AA is reserved FB_TA must be asserted by the external system regardless of the number of generated wait states In that case the external transfer acknowledge ends the cycle An external FB_TA supersedes the generation of an internal FB_TA 9 R...

Page 463: ...appropriate mode of byte enable support for these SRAMs 0 FB_BE BWE is not asserted for reads FB_BE BWE is asserted for data write only 1 FB_BE BWE is asserted for read and write accesses 4 BSTR Burst read enable Specifies whether burst reads are used for memory associated with each FB_CSn 0 Data exceeding the specified port size is broken into individual port sized non burst reads For example a l...

Page 464: ...s from other external chip select outputs after system reset After system reset FB_CS0 is asserted for every external access No other chip select can be used until the valid bit CSMR0 V is set at this point FB_CS0 functions as configured After this FB_CS 5 1 can be used as well At reset during parallel boot the logic levels on the FB_AD 4 3 signals determine global chip select port size During ser...

Page 465: ...ort sizes For example an 8 bit memory connects to the single lane FB_AD 31 24 FB_BE BWE0 A longword transfer through this 8 bit port takes four transfers starting with the MSB to the LSB A longword transfer through a 32 bit port requires one transfer on each four byte lane of the FlexBus Figure 20 4 Connections for External Memory Port Sizes 20 4 4 Address Data Bus Multiplexing The interface suppo...

Page 466: ...inues to be driven until one clock cycle after FB_CSn negates For a read transfer data is also driven into the device during this cycle External slave asserts FB_TA at this clock edge 3 S2 Read data and FB_TA are sampled on the third clock edge FB_TA can be negated after this edge and read data can then be tri stated 4 S3 FB_CSn is negated at the fourth rising clock edge This last clock of the bus...

Page 467: ...iven on FB_AD 31 X for writes and FB_AD 31 X is tristated for reads Address continues to be driven on the FB_AD pins that are unused for data If FB_TA is recognized asserted then the cycle moves on to S2 If FB_TA is not asserted internally or externally then the S1 state continues to repeat Read Data is driven by the external device before the next rising edge of FB_CLK the rising edge that begins...

Page 468: ...ternally terminated bus cycles NOTE The processor drives the data lines during the first clock cycle of the transfer with the full 32 bit address This may be ignored by standard connected devices using non multiplexed address and data buses However some applications may find this beneficial The address and data busses are muxed between the FlexBus and PCI controller At the end of the read bus cycl...

Page 469: ...ux d Bus FB_A 23 0 FB_D 31 X FB_AD 31 X FB_CSn FB_OE FB_BE BWEn FB_TA DATA DATA ADDR 23 0 ADDR 31 X ADDR 31 X ADDR Y 0 S0 FB_AD Y 0 1 Select the appropriate slave device Assert FB_TA external termination 3 1 Negate FB_TA external termination 1 Decode address 1 Set FB_R W to write Assert FB_CSn 2 1 auto acknowledge internal termination Sample FB_TA low 2 1 Start next cycle ColdFire device System Dr...

Page 470: ...ection shows timing diagrams for various port size scenarios Figure 20 10 illustrates the basic byte read transfer to an 8 bit device with no wait states The address is driven on the full FB_AD bus in the first clock The device tristates FB_AD on the second clock and continues to drive address on FB_CLK FB_R W FB_ALE FB_OE S0 S2 S3 DATA FB_TSIZ 1 0 TSIZ 1 0 S1 DATA Mux d Bus Non Mux d Bus FB_A 23 ...

Page 471: ...ransfer The data is driven from the second clock on FB_AD 31 24 Figure 20 11 Single Byte Write Transfer 23 0 FB_CLK S0 S1 S2 S3 FB_R W FB_ALE DATA 7 0 FB_TSIZ 1 0 01 DATA 7 0 Mux d Bus Non Mux d Bus FB_A 23 0 ADDR 23 0 ADDR 23 0 FB_D 31 24 ADDR 31 24 ADDR 31 24 FB_AD 23 0 FB_AD 31 24 FB_TA FB_CSn FB_OE FB_BE BWEn S0 FB_TA FB_CLK S0 S1 S2 S3 FB_R W FB_ALE FB_OE DATA 7 0 FB_TSIZ 1 0 01 DATA 7 0 Mux ...

Page 472: ...he address on FB_AD throughout the bus cycle The external device returns the read data on FB_AD 31 16 and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted Figure 20 12 Single Word Read Transfer 31 8 31 24 15 0 FB_CLK S0 S1 S2 S3 FB_AD 31 16 FB_R W FB_ALE FB_CSn FB_BE BWEn FB_TA FB_OE FB_AD 15 0 DATA 15 0 ADDR 15 0 FB_TSIZ 1 0 10 ADDR 31 16 DATA 15 0...

Page 473: ...32 bit device Figure 20 14 Longword Read Transfer FB_CLK S0 S1 S2 S3 FB_AD 31 16 FB_R W FB_ALE FB_TA FB_OE FB_CSn FB_BE BWEn DATA 15 0 FB_AD 15 0 ADDR 15 0 FB_TSIZ 1 0 10 ADDR 31 16 Mux d Bus Non Mux d Bus FB_D 31 16 DATA 15 0 FB_A 15 0 ADDR 15 0 ADDR 31 16 S0 FB_CLK S0 S1 S2 S3 FB_AD 31 0 FB_R W FB_ALE FB_TA FB_CSn FB_OE DATA 31 0 FB_TSIZ 1 0 00 ADDR 31 0 FB_D 31 0 DATA 31 0 ADDR 31 0 Mux d Bus N...

Page 474: ...ovide additional address setup address hold and time for a device to provide or latch data 20 4 6 4 1 Wait States Wait states can be inserted before each beat of a transfer by programming the CSCRn registers Wait states can give the peripheral or memory more time to return read data or sample write data FB_CLK S0 S1 S2 S3 FB_AD 31 0 FB_R W FB_ALE FB_TA FB_OE DATA 31 0 FB_TSIZ 1 0 00 ADDR 31 0 FB_D...

Page 475: ...20 17 Basic Write Bus Cycle No Wait States FB_CLK FB_R W FB_ALE S0 S1 S2 S3 DATA FB_TSIZ 1 0 TSIZ 1 0 DATA Mux d Bus Non Mux d Bus FB_A 23 0 ADDR 23 0 FB_D 31 X ADDR 31 X ADDR 31 X FB_AD Y 0 ADDR Y 0 FB_AD 31 X FB_CSn FB_OE FB_BE BWEn FB_TA S0 FB_TA FB_CLK FB_R W FB_ALE FB_OE S0 S1 S2 S3 DATA FB_TSIZ 1 0 TSIZ 1 0 DATA Mux d Bus Non Mux d Bus FB_A 23 0 ADDR 23 0 FB_D 31 X ADDR 31 X ADDR 31 X FB_AD ...

Page 476: ...te Figure 20 18 Read Bus Cycle One Wait State Figure 20 19 Write Bus Cycle One Wait State FB_CLK FB_R W FB_ALE S0 S1 WS S2 S3 DATA FB_TSIZ 1 0 TSIZ 1 0 DATA Mux d Bus Non Mux d Bus FB_A 23 0 ADDR 23 0 FB_D 31 X ADDR 31 X ADDR 31 X FB_AD Y 0 ADDR Y 0 FB_AD 31 X FB_CSn FB_OE FB_BE BWEn FB_TA S0 FB_CLK FB_R W FB_ALE FB_OE S0 S1 WS S2 S3 DATA FB_TSIZ 1 0 TSIZ 1 0 DATA Mux d Bus Non Mux d Bus FB_A 23 0...

Page 477: ... two clocks of address setup Figure 20 20 Read Bus Cycle with Two Clock Address Setup No Wait States Figure 20 21 Write Bus Cycle with Two Clock Address Setup No Wait States FB_CLK FB_R W FB_ALE S0 AS S1 S2 S3 DATA FB_TSIZ 1 0 TSIZ 1 0 DATA Mux d Bus Non Mux d Bus FB_A 23 0 ADDR 23 0 FB_D 31 X ADDR 31 X ADDR 31 X FB_AD Y 0 ADDR Y 0 FB_AD 31 X FB_CSn FB_OE FB_BE BWEn FB_TA S0 FB_CLK FB_R W FB_ALE F...

Page 478: ...e 20 22 Read Cycle with Two Clock Address Hold No Wait States Figure 20 23 Write Cycle with Two Clock Address Hold No Wait States FB_CLK FB_R W FB_ALE S0 S1 S2 S3 AH DATA FB_TSIZ 1 0 TSIZ 1 0 DATA Mux d Bus Non Mux d Bus FB_A 23 0 ADDR 23 0 ADDR 23 0 FB_D 31 X ADDR 31 X ADDR 31 X FB_AD 23 0 FB_AD 31 X FB_CSn FB_OE FB_BE BWEn FB_TA S0 FB_CLK FB_R W FB_ALE FB_OE S0 S1 S2 S3 AH DATA FB_TSIZ 1 0 TSIZ ...

Page 479: ...hroughout A longword transfer to an 8 bit port would take a 4 byte burst cycle for which FB_TSIZ 1 0 equals 00 throughout With bursting disabled any transfer larger than the port size breaks into multiple individual transfers With bursting enabled an access larger than port size results in a burst cycle of multiple beats Table 20 11 shows the result of such transfer translations Table 20 11 Transf...

Page 480: ...t address is driven throughout the entire burst for externally terminated cycles Figure 20 25 Longword Read Burst from 8 Bit Port 2 1 1 1 No Wait States Figure 20 26 shows a longword write to an 8 bit device with burst enabled The transfer results in a 4 beat burst and the data is driven on The transfer size is driven at longword 00 throughout the bus cycle NOTE The first beat of any write burst c...

Page 481: ...t longword 00 during the first transfer and at byte 01 during the next three transfers NOTE There is an extra clock of address setup AS for each burst inhibited transfer between states S0 and S1 FB_CLK FB_R W FB_ALE S0 S1 S2 S2 S2 S3 DATA DATA DATA DATA WS S2 FB_TSIZ 1 0 00 DATA DATA DATA DATA ADDR 1 ADDR 2 ADDR 3 Mux d Non Mux d Bus Bus FB_A 23 0 ADDR 23 0 ADDR 23 0 FB_D 31 24 31 24 ADDR FB_AD 23...

Page 482: ...FB_TSIZ 1 0 00 0101 FB_CLK FB_R W FB_ALE S0 S1 S2 S3 DATA DATA DATA DATA DATA AS S0 S1 S2 AS S0 S1 S2 AS S0 S1 S2 AS FB_TBST DATA DATA DATA DATA DATA ADDR 1 ADDR 2 ADDR 3 Mux d Non Mux d Bus Bus FB_A 23 0 ADDR 23 0 ADDR 23 0 FB_D 31 24 31 24 ADDR FB_AD 23 0 FB_AD 31 24 FB_CSn FB_OE FB_BE BWEn FB_TA S0 31 24 ADDR ...

Page 483: ...her read burst transfer but in this case a wait state is added between individual beats NOTE CSCRn WS determines the number of wait states in the first beat However for subsequent beats the CSCRn WS or CSCRn SWS if CSCRn SWSEN is set determines the number of wait states FB_CLK FB_R W FB_ALE S0 S1 S2 S3 DATA DATA DATA DATA DATA FB_TSIZ 1 0 00 0101 AS S0 S1 S2 AS S0 S1 S2 AS S0 S1 S2 AS DATA DATA DA...

Page 484: ...ATA DATA DATA DATA FB_TSIZ 1 0 00 DATA DATA DATA DATA ADDR 1 ADDR 2 ADDR 3 Mux d Non Mux d Bus Bus FB_A 23 0 ADDR 23 0 ADDR 23 0 FB_D 31 24 ADDR 31 24 ADDR 31 24 FB_AD 23 0 FB_AD 31 24 FB_CSn FB_OE FB_BE BWEn FB_TBST FB_TA S0 FB_CLK FB_R W FB_ALE S0 S1 WS S2 WS SWS S2 WS SWS S2 WS SWS S2 S3 DATA DATA DATA DATA FB_TSIZ 1 0 00 DATA DATA DATA DATA ADDR 1 ADDR 2 ADDR 3 Mux d Non Mux d Bus Bus FB_A 23 ...

Page 485: ...tire burst for externally terminated cycles Figure 20 31 Longword Read Burst from 8 Bit Port 3 1 1 1 Address Setup and Hold In multiplexed address data mode the address is driven on FB_AD only during the first cycle for internally and externally terminated cycles FB_CLK FB_R W FB_ALE S0 AS S1 S2 S2 S2 S2 S3 AH1 DATA DATA DATA DATA FB_TSIZ 1 0 11 DATA DATA DATA DATA ADDR 1 ADDR 2 ADDR 3 Mux d Non M...

Page 486: ...gword Write Burst to 8 Bit Port 3 1 1 1 Address Setup and Hold FB_CLK FB_R W FB_ALE S0 AS S1 S2 S2 S2 S2 S3 AH DATA DATA DATA FB_TSIZ 1 0 11 DATA DATA DATA DATA DATA ADDR 1 ADDR 2 ADDR 3 Mux d Non Mux d Bus Bus FB_A 23 0 ADDR 23 0 ADDR 23 0 FB_D 31 24 ADDR 31 24 ADDR 31 24 FB_AD 23 0 FB_AD 31 24 FB_CSn FB_OE FB_BE BWEn FB_TBST FB_TA S0 ...

Page 487: ...sor starts the second cycle a word transfers with a byte offset of 0x2 The next two bytes are transferred in this cycle In the third cycle byte 3 transfers The byte offset is now 0x0 the port supplies the final byte and the operation completes Example 20 1 A Misaligned Longword Transfer 32 Bit Port If an operand is cacheable and is misaligned across a cache line boundary both lines are loaded into...

Page 488: ...brief glossary and includes a description of signals involved in DRAM operations The remainder of the chapter describes the programming model and signal timing as well as the command set required for synchronous operations It also includes examples to better understand how to configure the DRAM controller for synchronous operations NOTE Unless otherwise noted in this chapter clock refers to the sy...

Page 489: ...n address lines 2 bits of bank address and two pinned out chip selects The maximum row bits plus column bits equals 25 in 16 bit bus mode Minimum memory configuration of 8 MByte 11 bit row address RA 9 bit column address CA 2 bit bank address BA 16 bit bus one chip select SD_CAS SD_WE SD_RAS Data out 63 0 ADDR Row Bank Column SD_BA 1 0 SD_A 13 0 Command Data in 63 0 SDRAM Controller State Machine ...

Page 490: ...cted through the SD_BA 1 0 signals SDRAM RAMs that operate like asynchronous DRAMs but with a synchronous clock a pipelined multiple bank architecture and a faster speed 21 2 External Signal Description This section introduces the signal names used in this chapter Table 21 1 SDRAM Interface Detailed Signal Descriptions Signal I O Description SD_A 13 0 O Memory multiplexed row column address Provid...

Page 491: ...nals are sent on the crossing of the positive edge of SD_CLK and the negative edge of SD_CLK Output data is referenced to the crossing of SD_CLK and SD_CLK both directions of crossing Timing Command signals occur synchronously with the rising edge of this clock Data signals can change on the rising and falling edge of the clock SD_CS 1 0 O SD_CS provides external bank selection on systems with mul...

Page 492: ...S frequency equals the memory clock frequency Data is normally 1 4 memory clock period after a DQS transition For DDR operation there is data following each DQS edge rising and falling for SDR operation valid data follows the rising edges only The address correspondence SD_DQS3 SD_D 31 24 SD_DQS2 SD_D 23 16 Note If a read is attempted from a DDR SDRAM chip select when there is no memory to respond...

Page 493: ...5 24 23 12 11 10 9 1 64 Mbits 4M x 16 bit 11 x 9 x 4 00 1 2 RA11 0 BA1 0 CA8 0 8M x 8 bit 12 x 9 x 4 00 16M x 4 bit 12 x 10 x 4 00 CA9 13 x 9 x 4 01 RA12 128 Mbits 8M x 16 bit 12 x 9 x 4 00 RA11 0 BA1 0 CA8 0 16M x 8 bit 12 x 10 x 4 00 CA9 13 x 9 x 4 01 RA12 32M x 4 bit 12 x 11 x 4 00 CA11 CA9 13 x 10 x 4 01 CA9 RA12 14 x 9 x 4 10 RA13 RA12 256 Mbits 16M x 16 bit 12 x 10 x 4 00 CA9 RA11 0 BA1 0 CA...

Page 494: ...32 M x 16 bit 12 x 11 x 4 00 CA11 CA9 RA11 0 BA1 0 CA8 0 13 x 10 x 4 01 CA9 RA12 14 x 9 x 4 10 RA13 RA12 64M x 8bit 12 x 12 x 4 00 CA12 CA11 CA9 13 x 11 x 4 01 CA11 CA9 RA12 14 x 10 x 4 10 CA9 RA13 RA12 1 Gbits 64M x 16bit 12 x 12 x 4 00 CA12 CA11 CA9 RA11 0 BA1 0 CA8 0 13 x 11 x 4 01 CA11 CA9 RA12 14 x 10 x 4 10 CA9 RA13 RA12 2 Gbits 128M x16bit 12 x 13 x 4 00 CA13 CA12 CA11 CA9 RA11 0 BA1 0 CA8 ...

Page 495: ...ilar routing to maintain timing integrity Control and clock signals are routed point to point Trace length for clock address and command signals should match Route DDR signals on layers adjacent to the ground plane Use a VREF plane under the SDRAM VREF is decoupled from SDVDD and VSS To avoid crosstalk address and command signals must remain separate from data and data strobes Use different resist...

Page 496: ...resistor pack 21 3 3 1 Termination Example Figure 21 3 shows the recommended termination circuitry for DDR SDRAM signals Figure 21 3 DDR SDRAM Termination Circuit 21 4 Memory Map Register Definition The SDRAM controller and its associated logic contain two sets of programming registers SDRAM controller s control and configuration registers Chip select configuration control registers NOTE The slew ...

Page 497: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BK AD 0 0 0 0 DDR2_AD W CMD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 4 SDRAM Mode Extended Mode Register SDMR Table 21 5 SDMR Field Descriptions Field Description 31 30 BK Bank address Driven onto SD_BA 1 0 along with a LMR LEMR command All SDRAM chip selects are asserted simultaneously SDCR CK...

Page 498: ...te operations Clear CKE to put the memory in self refresh or power down mode 0 SD_CKE is negated low 1 SD_CKE is asserted high 29 DDR_MODE DDR mode select Reserved 1 DDR mode 28 REF_EN Refresh enable 0 Automatic refresh disabled 1 Automatic refresh enabled 27 DDR2_MODE DDR2 mode select 0 DDR mode 1 DDR2 mode Note If DDR_MODE is cleared this bit is ignored 26 Reserved must be cleared 25 24 ADDR_MUX...

Page 499: ...DQSn signals and disable the other Then short both pins external to the device 1 SD_DQSn can drive as necessary depending on commands and SDCR OE_RULE setting DDR only 9 3 Reserved must be cleared 2 IREF Initiate refresh command Used to force a software initiated refresh command This bit is write only reads return zero 0 Do not generate a refresh command 1 Generate a refresh command All SD_CSn sig...

Page 500: ...2 SD_CLK memory controller clock is the speed of the SDRAM interface and is equal to the internal bus clock SD_CLK2 double frequency of SD_CLK DDR uses both edges of the bus frequency clock SD_CLK to read write data NOTE In all calculations for setting the fields of this register convert time units to clock units and round up to the nearest integer Address 0xFC0B_8008 SDCFG1 Access User read write...

Page 501: ...lue tRCD fSD_CLK 1 Round up to nearest integer Example If tRCD 20ns and fSD_CLK 99 MHz Suggested value 20ns 99 MHz 1 0 98 round to 1 Note Count value is in SD_CLK periods for DDR1 2 modes 15 Reserved must be cleared 14 12 PRE2ACT Precharge to active delay Precharge command to following active command delay counter Suggested value tRP fSD_CLK 1 Round up to nearest integer Example If tRP 20ns and fS...

Page 502: ... value is in SD_CLK2 periods 3 0 Reserved must be cleared Address 0xFC0B_800C SCFG2 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BRD2RP BWT2RWP BRD2W BL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 7 SDRAM Configuration Register 2 SDCFG2 Table 21 8 SDCFG2 Field Des...

Page 503: ...e appropriate DQS pulses the bus cycle hangs Because no high level bus monitor exists on the device a reset is the only way to exit the error condition Address 0xFC0B_8110 SDCS0 0xFC0B_8114 SDCS1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CSBA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSSZ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 504: ... Description 21 5 1 SDRAM Commands When an internal bus master accesses SDRAM address space the memory controller generates the corresponding SDRAM command Table 21 10 lists SDRAM commands supported by the memory controller 19 5 Reserved must be cleared 4 0 CSSZ Chip select size Table 21 10 SDRAM Commands Function Symbol CKE CS RAS CAS WE BA 1 0 A 10 Other A Command Inhibit INH H H X X X X X X No ...

Page 505: ...ow of an active bank it is a page hit and the read is issued as soon as possible pending any delays required by previous commands If the address is within an inactive bank the memory controller issues an ACTV followed by the read command If the address is not within the active row of an active bank the memory controller issues a pre command to close the active row Then the SDRAMC issues ACTV to ac...

Page 506: ... WRITE command to the SDRAM The PALL PRE and ACTV commands if necessary can sometimes be issued in parallel with an on going data movement With DDR memory a read command can be issued overlapping the masked beats at the end of a previous single write of the case CS the read command aborts the remaining unnecessary write beats 21 5 1 4 Burst Terminate Command BST SDRAMs are burst only devices but p...

Page 507: ... mode register and the mode register For DDR2 perform step 2 4 four times The first is for the third extended mode register second is for the second extended mode register third is for the first extended mode register the last is for the mode register 6 Clear the SDCR MODE_EN bit 21 5 1 6 1 Mode Register Definition Figure 21 9 shows a typical mode register definition This is the SDRAM s mode regis...

Page 508: ...e SDRAMC does not support interleaved bursts A2 A0 BLEN Burst length Determines the number of column locations that are accessed for a given READ or WRITE command 001 Two 010 Four 011 Eight Else Reserved BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Field 0 1 OPTION DLL Figure 21 10 Typical DDR Extended Mode Register Table 21 12 Typical DDR Extended Mode Register Field Descriptions Field Descripti...

Page 509: ... settings can vary from memory to memory A2 A0 PASR Partial array self refresh coverage 000 Full array 001 Half array 010 Quarter array 101 One eighth array 110 One sixteenth array All other settings are reserved BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Field 0 0 PD WR DLL TM CL BT BL Figure 21 12 DDR2 Mode Register Table 21 14 DDR2 Mode Register Field Descriptions Field Description BA1 B...

Page 510: ... 010 4 011 8 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Field 0 1 Qoff RDQS DQS OCD program Rtt Additive Latency Rtt D I C DLL Figure 21 13 DDR2 Extended Mode Register 1 Table 21 15 DDR2 Extended Mode Register 1 Field Descriptions Field Description BA1 BA0 Bank address Must be set to 01 to select the DDR2 Extended Mode Register 1 A12 Qoff Output buffer disabled Disables DQs DQSs DQSs RDQS R...

Page 511: ...die termination 00 ODT Disabled 01 75 ohm 10 150 ohm 11 Reserved A5 A3 Additive latency 000 0 001 1 010 2 011 3 100 4 Else Reserved A1 Output driver impedance control 0 Normal Driver size of 100 1 Weak Driver size of 60 A0 DLL enable 0 DLL Enable 1 DLL Disable Table 21 16 Strobe Function Matrix A11 RDQS Enable A10 DQS Enable Strobe Function Matrix RDQS DM RDQS DQS DQS 0 Disable 0 Enable DM Hi Z DQ...

Page 512: ...n self refresh mode a PALL and REF performs when the memory reactivates If the memory is put into and brought out of self refresh all within a single refresh interval the next automatic refresh occurs on schedule In self refresh mode memory does not require an external clock The SD_CLK can be stopped for maximum power savings If the memory controller clock is stopped the refresh interval timer mus...

Page 513: ...covery RCR Block The RCR block allows the external DDR memory devices to generate clock pulses strobes that define the data valid window for each DDR data cycle The RCR delay block compensates for each byte lane and generates an internal read strobe targeted to the center of the data valid window provided by the external DDR memories Figure 21 16 displays a simple timing diagram that illustrates t...

Page 514: ...ues for each chip select that is used 5 Program SDRAM configuration registers SDCFG1 and SDCFG2 with correct delay and timing values 6 Issue a PALL command Initialize the SDRAM control register SDCR with SDCR IPALL and SDCR MODE_EN set The SDCR REF and IREF bits should remain cleared for this step 7 Initialize the SDRAM s extended mode register to enable the DLL See Section 21 5 1 6 Load Mode Exte...

Page 515: ... IREF bits should remain cleared for this step 7 Refresh the SDRAM The SDRAM specification should indicate a number of refresh cycles to be performed before issuing an LMR command usually two Write to the SDCR with the IREF and MODE_EN bits set SDCR REF and IPALL must be cleared This forces a refresh of the SDRAM each time the IREF bit is set Repeat this step until the specified number of refresh ...

Page 516: ...REF bit is set Repeat this step until the specified number of refresh cycles have been completed 13 Initialize the SDRAM s mode register using the LMR command See Section 21 5 1 6 Load Mode Extended Mode Register Command lmr lemr for more instruction on issuing an LMR command During this step the OP_MODE field of the mode register should be set to normal operation 14 Set SDCR REF to enable automat...

Page 517: ... refresh cycle is started All SD_CS blocks are refreshed at the same time The refresh closes all banks of every SDRAM block 21 6 5 Transfer Size In the SDRAMC the internal data bus is 32 bits wide while the SDRAM external interface bus is 16 bits wide Therefore each internal data beat requires two memory data beats The SDRAM controller manages the size translation packing unpacking between interna...

Page 518: ...ation of the block NOTE The MCF54450 and MCF54451 devices do not contain a PCI bus controller 22 1 1 Block Diagram Figure 22 1 PCI Block Diagram 22 1 2 Overview The peripheral component interface PCI bus is a high performance bus with multiplexed address and data lines especially suitable for high data rate applications PCI Controller Configuration Interface Target Interface Initiator Interface Ex...

Page 519: ...system bus address translation Target response is medium PCI_DEVSEL generation Initiator latency time outs Memory prefetching of inbound PCI read accesses Supports posting of outbound and inbound PCI memory writes Automatic retry of target disconnects 22 1 4 Modes of Operation A host agent configuration parameter is provided at reset as a reset configuration signal See the Chapter 11 Chip Configur...

Page 520: ...multiplexed The PCI command is presented during the address phase and the byte enables are presented during the data phase Byte enables are active low Table 22 1 PCI Module External Signals Name Secondary1 1 Arbitration signal function when PCI Arbiter is disabled Function Type Reset PCI_AD 31 0 PCI Address Data Bus I O Tristate PCI_CLK PCI Clock I Toggling PCI_CBE 3 0 PCI Command Bytes Enables I ...

Page 521: ... active high during a PCI Type 0 configuration cycle to address the PCI configuration header 22 2 8 Interrupt PCI_INTA The PCI_INTA signal asserts active low by the PCI controller to request an interrupt 22 2 9 Initiator Ready PCI_IRDY The PCI_IRDY signal is asserted active low to indicate that the PCI initiator can transfer data During a write operation assertion indicates the master is driving v...

Page 522: ...n external PCI bus master can access internal memory space for register updates PCIGSCR PR bit controls PCI_RST and must first be cleared before external PCI devices wake up In other words an external PCI master cannot load configuration software across the PCI bus until software clears this bit Access to all internal registers is supported regardless of the value held in PCIGSCR PR Software reads...

Page 523: ...22 3 2 3 22 17 0xFC0A_806C PCI Target Control 1 Register PCITCR1 32 R W 0x0000_0008 22 3 2 4 22 18 0xFC0A_8070 PCI Initiator Window 0 Base Translation Address Register PCIIW0BTAR 32 R W 0x0000_0000 22 3 2 5 22 18 0xFC0A_8074 PCI Initiator Window 1 Base Translation Address Register PCIIW1BTAR 32 R W 0x0000_0000 22 3 2 5 22 18 0xFC0A_8078 PCI Initiator Window 2 Base Translation Address Register PCII...

Page 524: ...biter Registers 0xFC0A_C000 PCI Arbiter Control Register PACR 32 R W 0x8000_0000 22 3 3 1 22 26 0xFC0A_C004 PCI Arbiter Status Register PASR 32 R W 0x0000_0000 22 3 3 2 22 27 1 Alias of PCTBATR0 at location 0xFC0A_8090 2 Alias of PCTBATR1 at location 0xFC0A_8094 Address 0xFC0A_8000 PCIIDR Access User read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ...

Page 525: ... signalled This bit is set when the PCI controller generates a PCI system error on the PCI_SERR signal A PCI configuration cycle writing a 1 to the bit clears it Writing 0 has no effect 29 MA Master abort received Set when the PCI controller is the PCI master and terminates a transaction except for a special cycle with a master abort A PCI configuration cycle writing a 1 to the bit clears it Writi...

Page 526: ...t assert PCI_PERR 1 When a parity error is detected the PCI controller asserts PCI_PERR 5 V VGA palette snoop enable Fixed to 0 Indicates that the PCI controller is not VGA compatible Initialization software should write a 0 to this bit location 4 MW Memory write and invalidate enable Enables the MEMORY WRITE AND INVALIDATE command 0 Only MEMORY WRITE command can be used 1 PCI controller as master...

Page 527: ...e LTMR 7 3 LTMR 2 0 CLS 7 4 CLS 3 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 5 PCICR1 Register Table 22 6 PCICR1 Field Descriptions Field Description 31 24 BIST Built in self test Fixed to 0x00 The PCI controller does not implement the built in self test register Initialization software should write a 0x00 to this register location 23 16 Header Type Header ...

Page 528: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BAR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREF RANGE IO M W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Figure 22 7 PCIBAR1 Register Address 0xFC0A_8018 PCIBAR2 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BAR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREF RANGE IO M W Reset 0 0 0 ...

Page 529: ...BAR0 1 See corresponding PCIBARn figure above for bit numbers for the BARn and reserved bit fields Base address register n Applies only when the PCI controller is target These bits are programmable See Figures1 Reserved must be cleared 3 PREF Prefetchable access Indicates if memory space defined by BAR0 is prefetchable For PCIBAR0 this value is fixed to 0 while the other PCIBAR registers are fixed...

Page 530: ...00 at address 0xFC0A_8034 Address 0xFC0A_8028 PCICCPR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Pointer W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 12 PCICCPR Register Table 22 8 PCICCPR Field Descriptions Field Description 31 0 Pointer Pointer to the card information structure CIS for the Ca...

Page 531: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Figure 22 14 PCICR2 Register Table 22 10 PCICR2 Field Descriptions Field Description 31 24 Max_Lat Maximum latency Specifies how often in units of 1 4 microseconds the PCI controller would like to have access to the PCI bus as master A 0 value indicates the device has no stringent requirement in this area This field is programmable...

Page 532: ...ede to PCI_BARn target space Setting of this bit can trigger an interrupt request to the processor if the PCIGSCR DRDE bit is set 30 Reserved must be cleared 29 PE PCI_PERR detected Set when the PCI parity error signal PCI_PERR asserts any device A CPU interrupt is generated if the PCIGSCR PEE bit is set It is up to application software to clear this bit by writing 1 to it 28 SE SERR detected Set ...

Page 533: ... parity error is detected on the PCI_PERR signal When enabled and PCI_PERR asserts software must clear PCIGSCR PE to clear the interrupt condition 0 Interrupt disabled 1 Interrupt enabled 12 SEE SERR detected interrupt enable Enables CPU interrupt generation when a PCI system error is detected on the PCI_SERR signal When enabled and PCI_SERR asserts software must clear PCIGSCR SE to clear the inte...

Page 534: ...initialization sequence only 17 1 Reserved must be cleared 0 EN Enable 0 Enables a transaction in BAR0 space If this bit is zero and a hit on the PCI address space indicated by PCIBAR0 occurs the target interface gasket aborts the PCI transaction Address 0xFC0A_8068 PCITBATR1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BAT1 0 0 0 0...

Page 535: ... invalid This bit is sticky and completely disables prefetching from the internal bus for PCI when set This applies to MEMORY READ MULTIPLE as well as MEMORY READ and MEMORY READ LINE commands This bit must be cleared for the prefetch buffers to work 16 P Prefetch reads Controls fetching a line from memory in anticipation of request from the external master The target interface continues to prefet...

Page 536: ...t Bit 16 masks bit 24 bit 17 masks bit 25 and so on 0 Corresponding address bit used in address decode 1 Corresponding address bit ignored in address decode For internal bus accesses to the window n address range this byte also determines which upper 8 bits of the internal bus address to pass on for presentation as a PCI address Any address bit used to decode the internal bus address indicated by ...

Page 537: ...nternal bus initiator interface access to PCI for this window are initialized and used The PCI controller can begin to decode internal bus PCI accesses 0 Do not decode internal bus PCI accesses to window 1 Registers initialized decode accesses to window 23 20 Reserved must be cleared 19 16 W1C Window 1 control See W0C bit for field description 15 12 Reserved must be cleared 11 8 W2C Window 2 contr...

Page 538: ...itely and therefore permanently tie up the PCI bus if no target abort occurs Address 0xFC0A_8088 PCIISR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 RE IA TA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W w1c1 w1c1 w1c1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bits 26 24 are write one to c...

Page 539: ...enable Enables use of each target BAR register Value of reset configuration pins determines the enable register reset value and number BAR registers implemented at reset If programmed to 1 the respective BAR registers implement If low use of the BAR register is disabled Initialization software can enable desired BAR registers any time before PCI enumeration 7 1 Reserved must be cleared 0 CR Config...

Page 540: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 27 PCITBATR2 Register Address 0xFC0A_809C PCITBATR3 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BAT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 541: ... indicated by PCIBAR0 occurs the target interface gasket targets abort the PCI transaction Address 0xFC0A_80A8 PCIINTR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 31 PCIINTR Register Ta...

Page 542: ... I O transaction 1 Enabled Subsequent access to initiator window space defined as I O in the PCIIWCR register translates into a PCI configuration special cycle or interrupt acknowledge access using the configuration address register information Section 22 4 3 2 Configuration Mechanism 30 24 Reserved must be cleared 23 16 Bus Number Bus number Selects the target bus of the configuration access For ...

Page 543: ...upt enables If an external master time out occurs and the corresponding interrupt enable bit is set a CPU interrupt generates Bit 20 is the enable for PASR bit 20 bit 19 for PASR bit 19 and so on 0 Disable interrupt 1 Enable interrupt Software must write 1 to the corresponding PASR EXTMBK bit to clear the interrupt condition 16 INTMINTEN Internal master broken interrupt enable If a PCI Controller ...

Page 544: ...9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 EXTMBK ITLMBK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W w1c1 w1c1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bits 20 16 are write one clear w1c Hardware can set w1c bits but cannot clear them Software can clear w1c bits that are currently set by writing a 1 to the bit location Writing a 1 to a w1c bit that is currently a 0 or writing...

Page 545: ... MHz A system contains one device responsible for configuring all other devices on the bus upon reset Each device has 256 bytes of configuration space defining individual requirements to the system controller These registers are read and written through a CONFIGURATION ACCESS command The master starts a PCI transfer and is directed toward a specific target A provision is made for broadcasting to s...

Page 546: ...ME and PCI_IRDY are negated unless a fast back to back transaction is in progress In the case of a fast back to back transaction an address phase immediately follows the last phase 22 4 1 3 PCI Transactions The figures in this section show the basic MEMORY READ and MEMORY WRITE command transactions Figure 22 35 shows a PCI burst read transaction 2 beat The signal PCI_FRAME is driven low to initiat...

Page 547: ...TOP must remain asserted until PCI_FRAME negates The final data phase does not have to transfer data If PCI_STOP and PCI_IRDY are asserted while PCI_TRDY negates it is considered a target disconnect without a transfer See the PCI specification for more details Figure 22 36 PCI Write Terminated by Target Address Phase PCI_CLK PCI_FRAME PCI_AD PCI_CBE PCI_IRDY PCI_TRDY 0 1 2 3 4 5 6 7 8 PCI_DEVSEL D...

Page 548: ...EMORY READ command accesses agents mapped into PCI memory space 0111 MEMORY WRITE Yes Yes The MEMORY WRITE command accesses agents mapped into PCI memory space 1000 Reserved No No 1001 Reserved No No 1010 CONFIGURATION READ Yes Yes The CONFIGURATION READ command accesses the 256 byte configuration space of a PCI agent 1011 CONFIGURATION WRITE Yes Yes The CONFIGURATION WRITE command accesses the 25...

Page 549: ...ler supports linear incrementing and cache wrap mode When an internal bus burst transaction is wrapped for memory transactions the cache wrap mode automatically generates For zero word aligned bursts and single beat transactions the PCI controller drives AD 1 0 to 0b00 As a target PCI controller treats cache wrap mode as a reserved memory mode when the cache line size field is cleared PCICR1 CLS T...

Page 550: ...vice on the local PCI bus They do not propagate beyond the local PCI bus and are claimed by a local device or terminated with a master abort Type 1 configuration accesses target a device on a subordinate bus through a PCI to PCI bridge see Figure 22 39 Type 1 accesses are ignored by all targets except PCI to PCI bridges that pass the configuration request to another PCI bus When the controller ini...

Page 551: ... Type 1 Configuration Transaction Contents of the AD Bus During Address Phase During the address phase of a Type 1 configuration access the information on the AD bus is formatted as PCI_AD 1 0 contains 0b01 identifying this as a Type 1 configuration access PCI_AD 7 2 identifies one of 64 configuration Dwords within the target devices s configuration space PCI_AD 10 8 identifies one of the eight fu...

Page 552: ...for most devices on the PCI bus The PCI controller implements a Type 0 Configuration register set or header These registers discussed in Section 22 3 1 PCI Type 0 Configuration Registers are primarily intended to be read or written by the PCI configuring master at initialization time through the PCI bus The PCI controller provides internal access to these registers through an internal bus interfac...

Page 553: ...e provides a configuration address register which provides the ability to generate configuration interrupt acknowledge and special cycles This interface configures external PCI devices See Section 22 4 3 2 Configuration Mechanism for CONFIGURATION READ WRITE INTERRUPT ACKNOWLEDGE and SPECIAL CYCLE command support The internal bus initiator interface supports all internal bus transactions including...

Page 554: ... O configuration or special cycle the write connects The PCI controller gains access to the PCI bus and successfully transfers the data before it asserts address acknowledge to the internal bus If the address maps to PCI memory space the internal bus address phase immediately acknowledges and write data posts in a buffer in the PCI controller A 16 byte write buffer posts memory writes from interna...

Page 555: ...EDGE and SPECIAL CYCLE transactions See Section 22 4 3 3 Interrupt Acknowledge Transactions and Section 22 4 3 4 Special Cycle Transactions for more information If the bus number corresponds to the local PCI bus bus number equals 0x00 a Type 0 configuration cycle transaction performs If the bus number indicates a remote PCI bus PCI controller performs a Type 1 configuration cycle translation If th...

Page 556: ... AD12 0_1101 13 AD13 0_1110 14 AD14 0_1111 15 AD15 1_0000 16 AD16 1_0001 17 AD17 1_0010 18 AD18 1_0011 19 AD19 1_0100 20 AD20 1_0101 21 AD21 1_0110 22 AD22 1_0111 23 AD23 1_1000 24 AD24 1_1001 25 AD25 1_1010 26 AD26 1_1011 27 AD27 1_1100 28 AD28 1_1101 29 AD29 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E Reserved Bus Number Device Number Function Number D...

Page 557: ... Address Register PCICAR If the PCICAR E bit is set the bus number corresponds to the local PCI bus bus number equals 0x00 and the device number is all 1 s device number equals 0b1_1111 an INTERRUPT ACKNOWLEDGE transaction is initiated If the bus number indicates a subordinate PCI bus bus number equals 0x00 a Type 1 configuration cycle is initiated similar to any other configuration cycle the bus ...

Page 558: ...to a SPECIAL CYCLE command Master abort is the normal termination for a SPECIAL CYCLE and no errors report for this case of master abort termination This command is basically a broadcast to all agents and interested agents accept the command to process the request NOTE SPECIAL CYCLE commands do not cross PCI to PCI bridges If a master wants to generate a SPECIAL CYCLE command on a specific bus in ...

Page 559: ...evice selection timing only Six 16 byte buffers enhance data throughput The internal bus target interface provides access for external PCI masters to as many as six windows of internal processor address space The PCIBATR0 5 registers allow the user to map PCI address hits on the PCI controller s base address registers PCIBARn to areas in the internal address space At least one of these registers m...

Page 560: ...etching performs for BAR addressed transactions if the PCITCR1 PID bit clears and the PCI command is a MEMORY READ MULTIPLE or the PCITCR1 P bit is set When a delayed request latches and prefetching is enabled up to 16 bytes are fetched if possible The first 4 bytes is the delayed request and the next 28 bytes are prefetched This data is stored in the first cacheline size read buffer If no new tar...

Page 561: ...16 bytes of data store in this buffer and sent out on the internal bus as a complete 16 byte burst PCI write data must transfer with all byte enables enabled 32 bit to be buffered for a burst on the internal bus but can be combined from multiple consecutive PCI write transactions to complete the internal burst If a target write to a non sequential address or a target read occurs before an entire 3...

Page 562: ...01 OP2 10 OP3 0011 00 OP3 OP2 10 OP2 OP3 1000 00 OP3 OP2 OP1 00 OP1 OP2 10 OP3 0001 00 OP3 OP2 OP1 01 OP1 10 OP2 OP3 0000 00 OP3 OP2 OP1 OP0 00 OP0 OP1 OP2 OP3 Table 22 33 Non Contiguous PCI to Internal Bus Transfers All Require Two Internal Bus Accesses PCI Bus Internal Bus BE 3 0 AD 1 0 Data Bus Byte Lanes HADDR 1 0 Data Bus Byte Lanes 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 1010 00 OP3 OP2 00...

Page 563: ...rnal master to external target transactions as well as external master to PCI controller transactions 22 4 5 2 Hidden Bus Arbitration PCI bus arbitration can take place while the currently granted device performs a bus transaction if another master requests access to the bus As long as the bus is active the arbiter can deassert PCI_GNT to one master and assert PCI_GNT to the next in the same cycle...

Page 564: ...quest If the bus is idle when a device requests the bus the arbiter deasserts the currently asserted PCI_GNT for one PCI clock cycle The arbiter evaluates the priorities of all requesting devices and grants the bus to the highest priority device in the next cycle Figure 22 41 shows the initial state of the arbitration algorithm Two devices are assigned high priority the internal and one external m...

Page 565: ...PCI_GNT asserts the master must wait for the current transaction to complete and any subsequent transactions from higher priority requesting masters In a situation where multiple requesting masters exist each master latency timer limits the master s tenure on the bus 22 4 5 5 Arbitration Examples Figure 22 42 shows basic arbitration Three master devices illustrate how an arbiter may alternate bus ...

Page 566: ...0 completes its transaction on clock 5 and relinquishes the PCI bus On clock 6 device 1 detects the PCI bus is idle PCI_FRAME and PCI_IRDY deasserted and because its PCI_GNT remains asserted initiates the next transaction in the next cycle To indicate it only requires this single transaction on the PCI bus device 1 deasserts PCI_REQ on the same cycle it asserts PCI_FRAME Because device 0 is the on...

Page 567: ...e access 1 remains in progress the arbiter determines device 2 is higher priority than device 0 after device 1 access rearbitrates and deasserts PCI_GNT to device 0 and asserts PCI_GNT to device 2 in the next cycle clock 10 22 4 5 6 Bus Parking Bus parking asserts PCI_GNT to a PCI master while the PCI bus is idle and there are no incoming requests While the bus parks on a master the master must dr...

Page 568: ...PCI_GNT to the PCI controller in absence of any requests from other masters during the transaction the current master is forced to relinquish the bus if its master latency timer exhausts before all data transfers complete It would then have to wait two clocks and re arbitrate for the bus again to resume the transaction at the point where it left off When the PCI controller comes out of reset the i...

Page 569: ...y an external source to input to the PCI_CLK signal to generate an internal PCI clock The device uses this clock as its VCO reference clock The internal PLL generates the internal PCI clock and all other clocks for the system The PCIGSCR register reflects the PLL programmed ratios The PCI bus clock to external PCI devices generates from an external PLL while the internal PCI clock generates from t...

Page 570: ...put Another way to force interrupt to a level low is to disable the interrupt enable that corresponds to the asserted status bit The status bit however remains set 22 4 8 Reset Processor s system reset provides reset capability This signal resets hardware and software registers in the internal PCI arbiter A bit in the register space PCIGSCR PR controls PCI_RST During the system reset this bit is s...

Page 571: ...nsaction Internal Bus Slave Interface Cache Line Size PCICR1 CLS 4 Initiator Register Settings PCI Transaction Controller Internal Bus Initiator Interface PCI Target Initiator Window Configuration PCIIWCR Configuration Address Register PCICAR IO M PRC E Device Number 1_1111 Single Beat 1 4 byte Read x 0 00 x x MEMORY READ Burst Read 16 bytes x 0 00 x x MEMORY READ Single Beat 1 4 byte Read x 0 01 ...

Page 572: ...ddress mask values define the upper byte of address to decode The internal bus address space dedicated to PCI transactions can be mapped to three 16 Mbyte or larger address spaces in the device Initiator windows can be programmed to overlap though not recommended Priority for the windows is 0 1 2 Initiator window 0 has priority over all others and window 1 has priority over window 2 In normal oper...

Page 573: ...CI controller 0 4G 3G 2G 1G PCI Space Window 2 Internal Bus Initiator Windows 0 4G 3G 2G 1G 0 4G 3G 2G 1G 0 4G 3G 2G 1G PCI Controller Window 2 Window 0 Window 0 Window 0 Translation Window 1 Window 1 Translation Window 1 Not Recommended Window 2 Translation Not Recommended Window 2 Base Address 0x80 Window 2 Address Mask 0x3F Window 2 Translation Address 0xC0 Window 0 Base Address 0x40 Window 0 A...

Page 574: ...gister Register Function PCI Bus Configuration Access Processor Access Any Internal Bus Master Access PCIBARn PCI Base Address Register n X X X PCITBATRn PCI Target Base Address Translation Register n X X PCIIWnBTAR Initiator Window Base Translation Address Register n X X Table 22 38 Status Register Summary Status Register Register Function Internal Bus Target Interface Internal Bus Initiator Inte...

Page 575: ...PCI Bus Controller 22 58 Freescale Semiconductor ...

Page 576: ... disc drives and ATAPI optical disc drives It interfaces with the ATA device over a number of ATA signals The ATA interface is compliant to the ATA 6 standard and supports the following protocols PIO mode 0 1 2 3 and 4 Multiword DMA mode 0 1 and 2 Ultra DMA modes 0 1 2 3 and 4 with bus clock of 50 MHz or higher Ultra DMA mode 5 with bus clock of 80 Mhz or higher The ATA interface has 2 busses conn...

Page 577: ...exing and Control prior to configuring the ATA 23 1 2 Features The ATA interface has these features Programmable timing on the ATA bus Works with wide range of bus frequencies Compliant with AT Attachment 6 with Packet Interface specification found at http www t13 org Supports programmed input output PIO modes 0 1 2 3 and 4 Supports multiword DMA modes 0 1 and 2 Supports ultra DMA modes 0 1 2 3 4 ...

Page 578: ... of at least one packet of data waiting in the FIFO to be read by the host DMA When this alarm is asserted the host DMA should transfer one packet of data from FIFO to the main memory Typical packet size is 32 bytes 8 longwords but other packet sizes can be managed too FIFO transmit alarm informs the host DMA unit of space for at least one packet to be written by the host DMA When this alarm is as...

Page 579: ... signal DIOW During PIO and multiword DMA transfer function is write strobe During ultra DMA burst function is STOP signalling when host wants to terminate running ultra DMA transfer 23 2 1 4 ATA Chip Selects ATA_CS 1 0 These output signals are the chip selects for the ATA bus 23 2 1 5 ATA Address Lines ATA_DA 2 0 These output signals are the address lines of the ATA bus 23 2 1 6 ATA DMA Request A...

Page 580: ...PIO timing register 8 R W 0x01 23 3 2 23 7 0x9000_0006 TIME_PIORDX trd PIO timing register 8 R W 0x01 23 3 2 23 7 0x9000_0007 TIME_4 t4 PIO timing register 8 R W 0x01 23 3 2 23 7 0x9000_0008 TIME_9 t9 PIO timing register 8 R W 0x01 23 3 2 23 7 0x9000_0009 TIME_M tm MDMA timing register 8 R W 0x01 23 3 2 23 7 0x9000_00A TIME_JN tn and tj MDMA timing register 8 R W 0x01 23 3 2 23 7 0x9000_000B TIME_...

Page 581: ...0_0030 ATA_ICR Interrupt clear register 8 W Undefined 23 3 6 3 23 12 0x9000_0034 FIFO_ALARM FIFO alarm threshold 8 R W 0x00 23 3 7 23 12 Drive Registers 0x9000_00A0 DRIVE_DATA Drive data register 16 R W See Spec1 23 3 8 23 12 0x9000_00A4 DRIVE_FEATURES Drive features register 8 R W See Spec1 23 3 8 23 12 0x9000_00A8 DRIVE_SECTOR_COUNT Drive sector count register 8 R W See Spec1 23 3 8 23 12 0x9000...

Page 582: ...t register or as a 32 bit register Any longword write to the register puts the four bytes written into the FIFO and any Address 0x9000_0000 TIME_OFF 0x9000_0001 TIME_ON 0x9000_0002 TIME_1 0x9000_0003 TIME_2W 0x9000_0004 TIME_2R 0x9000_0005 TIME_AX 0x9000_0006 TIME_PIO_RDX 0x9000_0007 TIME_4 0x9000_0008 TIME_9 0x9000_0009 TIME_M 0x9000_000A TIME_JN 0x9000_000B TIME_D 0x9000_000C TIME_K 0x9000_000D ...

Page 583: ...ent number of halfwords present in the FIFO 23 3 5 ATA Control Register ATA_CR See Figure 23 6 for illustration of valid bits in the ATA control register and Table 23 4 for description of the bit fields Address 0x9000_00018 FIFO_DATA32 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FIFO_DATA W Reset Figure 23 3 FIFO Data Register in 3...

Page 584: ...REFILL FIFO transmit enable Controls if the FIFO makes transmit data requests to the DMA If enabled the FIFO requests the DMA to refill it when FIFO filling drops below the alarm level 0 FIFO refill by DMA disabled 1 FIFO refill by DMA enabled 4 FEMPTY FIFO receive enable Controls if the FIFO makes receive data requests to the DMA If enabled the FIFO requests the DMA to empty it whenr FIFO filling...

Page 585: ...t Status Register ATA_ISR Table 23 5 ATA_ISR Field Descriptions Field Description 7 DMA ATA DMA request Reflects the value of the ATA_INTRQ interrupt input signal When this bit is set in the ATA_ISR and ATA_IER registers the DMA end of transfer request is sent The interrupt clear register ATA_ICR has no influence on this bit 0 ATA_INTRQ negated 1 ATA_INTRQ asserted 6 FUF FIFO underfow Sticky bit t...

Page 586: ...nfluence on this bit 0 ATA_INTRQ negated 1 ATA_INTRQ asserted 2 0 Reserved Address 0x9000_002C ATA_IER Access User read write 7 6 5 4 3 2 1 0 R DMA FUF FOF IDLE INT W Reset 0 0 0 0 0 Figure 23 8 ATA_IER Register Table 23 6 Interrupt Enable Register Field Description Field Description 7 DMA ATA DMA request enable 0 ATA DMA request disabled 1 ATA DMA request enabled 6 FUF FIFO underfow interrupt ena...

Page 587: ...e not present in ATA interface module Table 23 2 provides a list of these registers If a read or write access is made to one of these registers read or write maps to a PIO read or write cycle on the ATA bus and the corresponding register in the device attached to the ATA bus Address 0x9000_0030 ATA_ICR Access User write only 7 6 5 4 3 2 1 0 R W FUF FOF Reset Figure 23 9 ATA_ICR Register Table 23 7...

Page 588: ...s described in detail in the following sections 23 4 1 Timing on ATA Bus Timing on the ATA bus is explained in this section with timing diagrams and equations 23 4 1 1 PIO Mode Timing Diagrams A timing diagram for PIO read mode appears in Figure 23 11 Figure 23 11 PIO Read Mode Timing To fulfill read mode timing the different timing parameters appearing in Table 23 8 must be observed Table 23 8 Ti...

Page 589: ...x 0 5 T tsu thi tskew3 tskew4 TIME_PIO_RDX t0 t0 min time_1 time_2 time_9 T TIME_1 TIME_2R TIME_9 1 See Figure 23 11 Table 23 9 Timing Parameters PIO Write ATA Parameter PIO Write Mode Timing Parameter1 Value How to meet t1 t1 t1 min time_1 T tskew1 tskew2 tskew5 TIME_1 t2 t2w t2 min time_2w T tskew1 tskew2 tskew5 TIME_2W t9 t9 t9 min time_9 T tskew1 tskew2 tskew6 TIME_9 t3 t3 min time_2w time_on ...

Page 590: ...4 tA tA tA 1 5 time_ax T tco tsui tcable2 tcable2 2 tbuf TIME_AX t0 t0 min time_1 time_2 time_9 T TIME_1 TIME_2R TIME_9 Avoid bus contention when switching buffer on by making ton long enough Avoid bus contention when switching buffer off by making toff long enough 1 See Figure 23 12 Table 23 9 Timing Parameters PIO Write continued ATA Parameter PIO Write Mode Timing Parameter1 Value How to meet A...

Page 591: ...n ti min time_m T tskew1 tskew2 tskew5 TIME_M td td td1 td1 min td min time_d T tskew1 tskew2 tskew6 TIME_D tk tk tk min time_k T tskew1 tskew2 tskew6 TIME_K t0 t0 min time_d time_k T TIME_D TIME_K tg read tgr tgr min read tco tsu tbuf tbuf tcable1 tcable2 tgr min drive td te drive TIME_D tf read tfr tfr min drive 0k tg write tg min write time_d T tskew1 tskew2 tskew5 TIME_D tf write tf min write ...

Page 592: ...iagram Figure 23 16 shows timing for host terminating UDMA in transfer Figure 23 16 UDMA in Host Terminates Transfer ATA_DA 2 0 ATA_DIOR Read Data ATA_DMACK ATA_DMARQ tc1 tds ATA_DIOW ATA_IORDY tc1 tdh tenv tack ATA_DA 2 0 ATA_DIOR Read Data ATA_DMACK ATA_DMARQ tc1 tds ATA_DIOW ATA_IORDY tc1 tdh trp tack tx1 tmli Write Data tdzfs tcvh toff ton tzah ATA_BUFFER_EN ...

Page 593: ... enough trp trp trp min time_rp T tskew1 tskew2 tskew6 TIME_RP tx11 1 There is a special timing requirement in the ATA host requiring the internal DIOW to only go high three clocks after the last active edge on the DSTROBE signal The equation on this line tries to capture this constraint 2 Make ton and toff big enough to avoid bus contention time_rp T tco tsu 3T 2 tbuf 2 tcable2 trfs drive TIME_RP...

Page 594: ... shows timing for UDMA out transfer start Figure 23 18 UDMA Out Transfer Start Timing Diagram Figure 23 19 shows timing for host terminating UDMA out transfer Figure 23 19 UDMA Out Host Terminates Transfer Figure 23 20 shows timing for device terminating UDMA out transfer ATA_DA 2 0 ATA_DMARQ ATA_DMACK ATA_DIOW ATA_DIOR ATA_BUFFER_EN Write Data ATA_IORDY ATA_DA 2 0 ATA_DMARQ ATA_DMACK ATA_DIOW ATA...

Page 595: ... tdvs tdvs tdvs time_dvs T tskew1 tskew2 TIME_DVS tdvh tdvh tdvs time_dvh T tskew1 tskew2 TIME_DVH tcyc tcyc tcyc time_cyc T tskew1 tskew2 TIME_CYC t2cyc t2cyc time_cyc 2 T TIME_CYC trfs1 trfs trfs 1 6 T tsui tco tbuf tbuf tdzfs tdzfs time_dzfs T tskew1 TIME_DZFS tss tss tss time_ss T tskew1 tskew2 TIME_SS tmli tdzfs_mli tdzfs_mli max time_dzfs time_mli T tskew1 tskew2 tli tli1 tli1 0 tli tli2 tli...

Page 596: ... change the bus clock period Dynamic voltage frequency scaling Wait for ATA_ISR IDLE because a PIO read or write to the ATA bus terminates after the bus cycle with the CPU terminates If the wait for ATA_ISR IDLE does not occur the new timing values may affect a running bus cycle and cause error The ATA_CR IORDYEN bit influences whether the ATA interface responds to the iordy signal coming from the...

Page 597: ... attention to DMA when there is at least one packet ready for transfer 5 To make the ATA ready for a DMA transfer from device to host take the following steps a Make sure the FIFO is enabled by setting the ATACR FEN bit b Set the ATA_CR FEMPTY bit which enables the FIFO to by emptied by the DMA c Program ATA_CR DMAPEND equals 1 and ATA_CR DMADIR equals 0 Also select the DMA mode ATA_CR DMAMODE equ...

Page 598: ...rammed 2 Make sure the FIFO is empty by reading it until empty or by resetting it 3 Initialize the DMA channel associated with ATA transmit Every time ATA transmit DMA request asserts the DMA should read packetsize longwords from the main memory and write them to the FIFO typical packetsize is 8 longwords Program the DMA so it does not transfer more than sectorsize longwords in total 4 Write FIFO_...

Page 599: ... monitor for end of transfer by reading some device ATA registers These reads cause the running DMA to pause after the read completes the DMA resumes The host can also wait until the drive asserts ATA_INTRQ This also indicates end of transfer On end of transfer no extra FIFO manipulations are needed ...

Page 600: ...Advanced Technology Attachment ATA Freescale Semiconductor 23 25 ...

Page 601: ...Freescale Semiconductor 1 ...

Page 602: ...ons in hardware to increase the throughput of software based encryption and hashing functions 24 1 1 Block Diagram Figure 24 1 shows a simplified block diagram of the CAU Figure 24 1 Top Level CAU Block Diagram 24 1 2 Overview The CAU supports acceleration of the following algorithms DES 3DES AES MD5 ALU CAA CAx DES CA0 CA3 Register File Operand1 Result Decode Command Hash Go Datapath Control AES ...

Page 603: ...nts a set of 22 coprocessor commands that operate on a register file of eight 32 bit registers It is tightly coupled to the ColdFire core and there is no local memory or external interface 24 1 3 Features The CAU includes these distinctive features Supports DES 3DES AES MD5 SHA 1 algorithms Simple flexible programming model 24 2 Memory Map Register Definition The CAU only supports longword operati...

Page 604: ...ptions Field Description 31 28 VER CAU version Indicates CAU version 0x1 Initial CAU version This is the value on this device 0x2 Second version added support for SHA 256 algorithm 27 2 Reserved must be cleared 1 DPE DES parity error 0 No error detected 1 DES key parity error detected 0 IC Illegal command Indicates an illegal instruction not found in Section 24 3 3 CAU Commands has been executed 0...

Page 605: ...es CAU operations The store instruction stores CAU registers The example assembler syntax for the CAU is cp0ld l ea CMD coprocessor load cp0st l ea CMD coprocessor store The ea field specifies the source operand operand1 for load instructions and destination result for store instructions The basic ColdFire addressing modes Rn An An An d16 An are supported for this field The CMD field is a 9 bit va...

Page 606: ...CAx CAx CAA CAA cp0ld XOR Exclusive Or 0x06 CAx CAx Op1 CAx cp0ld ROTL Rotate Left 0x07 CAx CAx Op1 CAx cp0ld MVRA Move Reg to Acc 0x08 CAx CAx CAA cp0ld MVAR Move Acc to Reg 0x09 CAx CAA CAx cp0ld AESS AES Sub Bytes 0x0A CAx SubBytes CAx CAx cp0ld AESIS AES Inv Sub Bytes 0x0B CAx InvSubBytes CAx CAx cp0ld AESC AES Column Op 0x0C CAx MixColumns CAx Op1 CAx cp0ld AESIC AES Inv Column Op 0x0D CAx In...

Page 607: ...not actually issued to the coprocessor from the core 24 3 3 2 Load Register LDR cp0ld l ea LDR CAx The LDR command loads CAx with the source data specified by ea 24 3 3 3 Store Register STR cp0st l ea STR CAx The STR command stores the value from CAx to the destination specified by ea 24 3 3 4 Add to Register ADR cp0ld l ea ADR CAx The ADR command adds the source operand specified by ea to CAx and...

Page 608: ...on register CAx 24 3 3 11 AES Substitution AESS cp0ld l AESS CAx The AESS command performs the AES byte substitution operation on CAx and stores the result back to CAx 24 3 3 12 AES Inverse Substitution AESIS cp0ld l AESIS CAx The AESIS command performs the AES inverse byte substitution operation on CAx and stores the result back to CAx 24 3 3 13 AES Column Operation AESC cp0ld l ea AESC CAx The A...

Page 609: ...forms on CA2 and CA3 before the round operation If the FP bit is set DES final permutation inverse initial permutation performs on CA2 and CA3 after the round operation The round operation uses the source values from registers CA0 and CA1 for the key addition operation The KSx field specifies the shift for the key schedule operation to update the values in CA0 and CA1 Table 24 9 defines the specif...

Page 610: ...ld l HASH HFx The HASH command performs a hashing operation on a set of registers and adds that result to the value in CAA and stores the result in CAA The specific hash function performed is based on the HFx field as defined in Table 24 10 24 3 3 20 Secure Hash Shift SHS cp0ld l SHS The SHS command does a set of parallel register to register move and shift operations for implementing SHA 1 The fo...

Page 611: ...n example of how the CAU is used This example shows the round function of the AES algorithm Core register A0 is pointing to the key schedule cp0ld l AESS CA0 sub bytes w0 cp0ld l AESS CA1 sub bytes w1 cp0ld l AESS CA2 sub bytes w2 cp0ld l AESS CA3 sub bytes w3 cp0ld l AESR shift rows cp0ld l a0 AESC CA0 mix col add key w0 cp0ld l a0 AESC CA1 mix col add key w1 cp0ld l a0 AESC CA2 mix col add key w...

Page 612: ...tation set FP 0x04 final permutation set KSL1 0x00 key schedule left 1 bit set KSL2 0x01 key schedule left 2 bits set KSR1 0x02 key schedule right 1 bit set KSR2 0x03 key schedule right 2 bits DESK Field set DC 0x01 decrypt key schedule set CP 0x02 check parity HASH Functions Codes set HFF 0x0 MD5 F CA1 CA2 CA1 CA3 set HFG 0x1 MD5 G CA1 CA3 CA2 CA3 set HFH 0x2 MD5 H SHA Parity CA1 CA2 CA3 set HFI ...

Page 613: ...ropy needed to create random data CAUTION There is no known cryptographic proof showing that this is a secure method of generating random data In fact there may be an attack against the random number generator if its output is used directly in a cryptographic application the attack is based on the linearity of the internal shift registers In light of this it is highly recommended to use the random...

Page 614: ...ster RNGCR 32 R W 0x0000_0000 25 2 1 25 2 0xFC0B_4004 RNG Status Register RNGSR 32 R 0x0010_0000 25 2 2 25 3 0xFC0B_4008 RNG Entropy Register RNGER 32 W 0x0000_0000 25 2 3 25 4 0xFC0B_400C RNG Output FIFO RNGOUT 32 R 0x0000_0000 25 2 4 25 4 0xFC0B_4000 RNGCR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 615: ...0 0 0 0 0 0 0 0 Figure 25 2 RNG Status Register RNGSR Table 25 3 RNGSR Field Descriptions Field Description 31 24 Reserved must be cleared 23 16 OFS Output FIFO size Indicates size of the output FIFO 16 words and maximum possible value of RNGR OFL 15 8 OFL Output FIFO level Indicates current number of random words in the output FIFO Determines if valid random data is available for reading from the...

Page 616: ...gister RNGSR can be polled to monitor how many 32 bit words are currently resident in the FIFO A new random word pushes into the FIFO every 256 clock cycles as long as the FIFO is not full It is very important to poll RNGSR OFL to make sure random values are present before reading from RNGOUT 1 LRS Last read status Reflects status of most recent read of the FIFO 0 During last read FIFO was not emp...

Page 617: ...RNG Core Control Logic Block This block contains the RNG s control logic as well as its core engine that generates random data 25 3 2 1 RNG Control Block The control block contains the address decoder all addressable registers and control state machines for the RNG This block is responsible for communication with the peripheral interface and the FIFO interface The block also controls the core engi...

Page 618: ...ator clocks are turned on 25 4 Initialization Application Information The intended general operation of the RNG is as follows 1 Reset initialize 2 Write to the RNG entropy register optional 3 Write to the RNG control register and set the interrupt mask high assurance and GO bits 4 Poll RNGSR OFL to check for random data in the FIFO 5 Read available random data from RNGOUT 6 Repeat steps 3 and 4 as...

Page 619: ...Overview The Ethernet media access controller MAC supports 10 and 100 Mbps Ethernet IEEE 802 3 networks An external transceiver interface and transceiver function are required to complete the interface to the media The FECs support five different standard MAC PHY physical interfaces for connection to an external Ethernet transceiver The FECs support the 10 100 Mbps MII 10 100 Mbps reduced MII and ...

Page 620: ...ress recognition for receive frames Random number generation for transmit collision backoff timer Internal Bus Control Status FIFO FEC DMA Descriptor Controller MII Receive Transmit Bus Controller Controller RISC microcode I O PAD MDO MDEN MDI FIFO RAM FEC Bus FECn_COL FECn_RXCLK FECn_RXDV 1 FECn_TXCLK 2 FECn_MDC FECn_MDIO MII to RMII MII FECn_TXD0 FECn_TXEN FECn_RXD0 FECn_RXER FECn_TXD1 FECn_RXD1...

Page 621: ...nt data input output lines of the MII interface The FEC DMA block not to be confused with the device s eDMA controller provides multiple channels allowing transmit data transmit descriptor receive data and receive descriptor accesses to run independently The transmit and receive blocks provide the Ethernet MAC functionality with some assist from microcode The message information block MIB maintain...

Page 622: ...t and Section 26 5 11 Full Duplex Flow Control for more details 26 2 2 Interface Options The following interface options are supported A detailed discussion of the interface configurations is provided in Section 26 5 6 Network Interface Options 26 2 2 1 10 Mbps and 100 Mbps MII Interface The IEEE 802 3 standard defines the media independent interface MII for 10 100 Mbps operation The MAC PHY inter...

Page 623: ... and External Loopback 26 3 External Signal Description Table 26 1 describes the various FEC signals as well as indicating which signals work in available modes Table 26 1 FEC Signal Descriptions Signal Name MII 7 wire RMII Description FEC_COL X X Asserted upon detection of a collision and remains asserted while the collision persists This signal is not defined for full duplex mode FEC_CRS X Carri...

Page 624: ..._TXCLK X X X Input clock which provides a timing reference for FEC_TXEN FEC_TXD 3 0 and FEC_TXER In RMII mode this signal is the reference clock for receive transmit and the control interface FEC_TXD0 X X X The serial output Ethernet data and only valid during the assertion of FEC_TXEN FEC_TXD1 X X This pin contains the serial output Ethernet data and valid only during assertion of FEC_TXEN FEC_TX...

Page 625: ...4 8 26 17 0xFC03_0064 0xFC03_4064 MIB Control Status Register MIBCn 32 R W 0x0000_0000 26 4 9 26 18 0xFC03_0084 0xFC03_4084 Receive Control Register RCRn 32 R W 0x05EE_0001 26 4 10 26 19 0xFC03_00C4 0xFC03_40C4 Transmit Control Register TCRn 32 R W 0x0000_0000 26 4 11 26 21 0xFC03_00E4 0xFC03_40E4 Physical Address Low Register PALRn 32 R W Undefined 26 4 12 26 22 0xFC03_00E8 0xFC03_40E8 Physical A...

Page 626: ...n addition some of the recommended package objects supported do not require MIB counters Counters for transmit and receive full duplex flow control frames are also included 0xFC03_014C 0xFC03_414C FIFO Receive Bound Register FRBRn 32 R 0x0000_0600 26 4 20 26 26 0xFC03_0150 0xFC03_4150 FIFO Receive FIFO Start Register FRSRn 32 R 0x0000_0500 26 4 21 26 26 0xFC03_0180 0xFC03_4180 Pointer to Receive D...

Page 627: ...MON Tx 65 to 127 byte packets RMON_T_P65TO127n 0xFC03_0230 0xFC03_4230 RMON Tx 128 to 255 byte packets RMON_T_P128TO255n 0xFC03_0234 0xFC03_4234 RMON Tx 256 to 511 byte packets RMON_T_P256TO511n 0xFC03_0238 0xFC03_4238 RMON Tx 512 to 1023 byte packets RMON_T_P512TO1023n 0xFC03_023C 0xFC03_423C RMON Tx 1024 to 2047 byte packets RMON_T_P1024TO2047n 0xFC03_0240 0xFC03_4240 RMON Tx packets with 2048 b...

Page 628: ...tted without error IEEE_T_OCTETS_OKn 0xFC03_0280 0xFC03_4280 Count of received frames not counted correctly RMON_R_DROPn 0xFC03_0284 0xFC03_4284 RMON Rx packet count RMON_R_PACKETSn 0xFC03_0288 0xFC03_4288 RMON Rx broadcast packets RMON_R_BC_PKTn 0xFC03_028C 0xFC03_428C RMON Rx multicast packets RMON_R_MC_PKTn 0xFC03_0290 0xFC03_4290 RMON Rx packets with CRC Align error RMON_R_CRC_ALIGNn 0xFC03_02...

Page 629: ...0xFC03_02B0 0xFC03_42B0 RMON Rx 128 to 255 byte packets RMON_R_P128TO255n 0xFC03_02B4 0xFC03_42B4 RMON Rx 256 to 511 byte packets RMON_R_P256TO511n 0xFC03_02B8 0xFC03_42B8 RMON Rx 512 to 1023 byte packets RMON_R_P512TO1023n 0xFC03_02BC 0xFC03_42BC RMON Rx 1024 to 2047 byte packets RMON_R_P1024TO2047n 0xFC03_02C0 0xFC03_42C0 RMON Rx packets with 2048 bytes RMON_R_P_GTE2048n 0xFC03_02C4 0xFC03_42C4 ...

Page 630: ... following a transmission 30 BABR Babbling receive error Indicates a frame was received with length in excess of RCRn MAX_FL bytes 29 BABT Babbling transmit error Indicates the transmitted frame length exceeds RCRn MAX_FL bytes Usually this condition is caused by a frame that is too long is placed into the transmit data buffer s Truncation does not occur 28 GRA Graceful stop complete Indicates the...

Page 631: ...ontroller and DMA also soft reset 21 LC Late collision Indicates a collision occurred beyond the collision window slot time in half duplex mode The frame truncates with a bad CRC and the remainder of the frame is discarded 20 RL Collision retry limit Indicates a collision occurred on each of 16 successive attempts to transmit the frame The frame is discarded without being transmitted and transmiss...

Page 632: ...transmit descriptor ring and processes transmit frames provided ECRn ETHER_EN is also set After the FEC polls a transmit descriptor that is a ready bit not set FEC Table 26 6 EIMRn Field Descriptions Field Description 31 19 See Figure 26 3 and Table 26 5 Interrupt mask Each bit corresponds to an interrupt source defined by the EIRn register The corresponding EIMRn bit determines whether an interru...

Page 633: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 5 Transmit Descriptor Active Register TDARn Table 26 8 TDARn Field Descriptions Field Description 31 25 Reserved must be cleared 24 TDAR Set to 1 when this register is written regardless of the value written Cleared by the FEC device when no additional ready descriptors remain in the trans...

Page 634: ...set by software in which case ETHER_EN is cleared An error condition causes the EIRn EBERR bit to set in which case ETHER_EN is cleared 0 RESET When this bit is set the equivalent of a hardware reset is performed but it is local to the FEC ECRn ETHER_EN is cleared and all other FEC registers take their reset values Also any transmission reception currently in progress is abruptly aborted This bit ...

Page 635: ... the data in the MMFRn register following a preamble generated by the control state machine During this time contents of the MMFRn register are altered as the contents are serially shifted and are unpredictable if read by the user After the read management frame operation completes the MII interrupt is generated At this time the contents of the MMFRn register match the original value written excep...

Page 636: ...f the MIB block User software accesses this register if there is a need to disable the MIB block operation For example to clear all MIB counters in RAM 1 Disable the MIB block 2 Clear all the MIB RAM locations 3 Enable the MIB block Table 26 11 MSCR Field Descriptions Field Description 31 8 Reserved must be cleared 7 DIS_PRE Setting this bit causes the preamble 32 ones not to be prepended to the M...

Page 637: ...ters 30 MIB_IDLE A read only status bit If set the MIB block is not currently updating any MIB counters 29 0 Reserved Address 0xFC03_0084 RCR0 0xFC03_4084 RCR1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 MAX_FL W Reset 0 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 RMII_ ECHO RMII_ LOOP RMII_ 10T RMII_ MODE 0 0 FCE BC_ REJ PRO...

Page 638: ... operation The 50 MHz RMII reference clock on FEC_TXCLK is sent to the RMII while a divided by 2 version 25 MHz is sent to the FEC 1 10 Mbps operation The 50 MHz RMII reference clock on FEC_TXCLK is divided by 10 5 MHz and sent to the RMII while a divided by 20 version 2 5 MHz is sent to the FEC 8 RMII_MODE RMII Mode Indicates if the FEC is in RMII or MII 7 wire mode This is a read only bit that r...

Page 639: ...ernal to the device and transmit output signals are not asserted The internal bus clock substitutes for the FECn_TXCLK when LOOP is asserted DRT must be set to 0 when setting LOOP Address 0xFC03_00C4 TCR0 0xFC03_40C4 TCR1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFC_ PAUSE TF...

Page 640: ...set the heartbeat check performs following end of transmission and the HB bit in the status register is set if the collision input does not assert within the heartbeat window This bit should only be modified when ECRn ETHER_EN is cleared 0 GTS Graceful transmit stop When this bit is set MAC stops transmission after any frame currently transmitted is complete and GRA interrupt in the EIRn register ...

Page 641: ... and you must initialize it Address 0xFC03_00E8 PAUR0 0xFC03_40E8 PAUR1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PADDR2 TYPE W Reset 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 Figure 26 13 Physical Address Upper Register PAURn Table 26 17 PAURn Field Descriptions Field Description 31 16 PADDR2 Bytes 4 bits 31 24 and 5 bits 23 16 of the 6 b...

Page 642: ...pper Address Register IAURn Table 26 19 IAURn Field Descriptions Field Description 31 0 IADDR1 The upper 32 bits of the 64 bit hash table used in the address recognition process for receive frames with a unicast address Bit 31 of IADDR1 contains hash index bit 63 Bit 0 of IADDR1 contains hash index bit 32 Address 0xFC03_011C IALR0 0xFC03_411C IALR1 Access User read write 31 30 29 28 27 26 25 24 23...

Page 643: ...Description 31 0 GADDR1 The GADDR1 register contains the upper 32 bits of the 64 bit hash table used in the address recognition process for receive frames with a multicast address Bit 31 of GADDR1 contains hash index bit 63 Bit 0 of GADDR1 contains hash index bit 32 Address 0xFC03_0124 GALR0 0xFC03_4124 GALR1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ...

Page 644: ...Hardware initializes the FRSRn register at reset FRSRn only needs to be written to change the default value Table 26 23 TFWRn Field Descriptions Field Description 31 2 Reserved must be cleared 1 0 TFWR Number of bytes written to transmit FIFO before transmission of a frame begins 00 64 bytes written 01 64 bytes written 10 128 bytes written 11 192 bytes written Address 0xFC03_014C FRBR0 0xFC03_414C...

Page 645: ... 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R_FSTART 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Figure 26 21 FIFO Receive Start Register FRSRn Table 26 25 FRSRn Field Descriptions Field Description 31 11 Reserved must be cleared 10 Reserved must be set 9 2 R_FSTART Address of first receive FI...

Page 646: ...bits 3 0 are forced low To minimize bus utilization descriptor fetches it is recommended that EMRBRn be greater than or equal to 256 bytes The EMRBRn register is undefined at reset and must be initialized by the user Address 0xFC03_0184 ETSDR0 0xFC03_4184 ETSDR1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R X_DES_START 0 0 W Reset Fi...

Page 647: ...roduces the buffer Software writing to TDARn or RDARn tells the FEC that a buffer is placed in external memory for the transmit or receive data traffic respectively The hardware reads the BDs and consumes the buffers after they have been produced After the data DMA is complete and the DMA engine writes the buffer descriptor status bits hardware clears RxBDn E or TxBDn R to signal the buffer has be...

Page 648: ...o TDARn When this register is written to data value is not significant the FEC RISC tells the DMA to read the next transmit BD in the ring After started the RISC DMA continues to read and interpret transmit BDs in order and DMA the associated buffers until a transmit BD is encountered with the R bit cleared At this point the FEC polls this BD one more time If the R bit is cleared the second time R...

Page 649: ...V and TR bits and writes the length of the used portion of the buffer in the first longword The M BC MC LG NO CR OV and TR bits in the first longword of the buffer descriptor are only modified by the Ethernet controller when the L bit is set 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset 0 E RO1 W RO2 L M BC MC LG NO CR OV TR Offset 2 Data Length Offset 4 Rx Data Buffer Pointer A 31 16 Offset 6 Rx D...

Page 650: ... frame that contained a number of bits not divisible by 8 was received and the CRC check that occurred at the preceding byte boundary generated an error This bit is valid only if the L bit is set If this bit is set the CR bit is not set Offset 0 3 Reserved must be cleared Offset 0 2 CR Receive CRC error Written by the FEC This frame contains a CRC error and is an integral number of octets in lengt...

Page 651: ...e data buffer prepared for transmission by you has not been transmitted or currently transmits You may write no fields of this BD after this bit is set Offset 0 14 TO1 Transmit software ownership This field is reserved for software use This read write bit is not modified by hardware nor does its value affect hardware Offset 0 13 W Wrap Written by user 0 The next buffer descriptor is found in the c...

Page 652: ...ftware to halt operation By clearing ECRn ETHER_EN configuration control registers such as the TCRn and RCRn are not reset but the entire data path is reset 26 5 3 User Initialization Prior to Setting ECRn ETHER_EN You need to initialize portions the FEC prior to setting the ECRn ETHER_EN bit The exact values depend on the particular application The sequence is not important Offset 4 15 0 A 31 16 ...

Page 653: ...ions Table 26 32 User Initialization Before ECRn ETHER_EN Description Initialize EIMRn Clear EIRn write 0xFFFF_FFFF TFWRn optional IALRn IAURn GAURn GALRn PALRn PAURn only needed for full duplex flow control OPDn only needed for full duplex flow control RCRn TCRn MSCRn optional Clear MIB_RAMn Table 26 33 FEC User Initialization Before ECR ETHER_EN Description Initialize FRSRn optional Initialize E...

Page 654: ...are 18 signals defined by the IEEE 802 3 standard and supported by the EMAC Table 26 35 shows these signals In RMII mode RCR MII_MODE set and RCR RMII_MODE cleared the EMAC supports 8 external signals These signals are shown in Table 26 36 below Initialize Transmit Ring Pointer Initialize Receive Ring Pointer Initialize FIFO Count Registers Table 26 35 MII Mode Signal Description EMAC pin Transmit...

Page 655: ...imiter SFD and then the frame information from the FIFO However the controller defers the transmission if the network is busy FECn_CRS is asserted Before transmitting the controller waits for carrier sense to become inactive then determines if carrier sense stays inactive for 60 bit times If so transmission begins after waiting an additional 36 bit times 96 bit times after carrier sense originally...

Page 656: ...mitter stops immediately if transmission is not in progress otherwise it continues transmission until the current frame finishes or terminates with a collision After the transmitter has stopped the GRA graceful stop complete interrupt is asserted If TCRn GTS is cleared the FEC resumes transmission with the next frame 26 5 7 1 Duplicate Frame Transmission The FEC fetches transmit buffer descriptors...

Page 657: ...ected the frame the receive FIFO signals the frame is accepted and may be passed on to the DMA If the frame is a runt due to collision or is rejected by address recognition the receive FIFO is notified to reject the frame Therefore no collision fragments are presented to you except late collisions which indicate serious LAN problems During reception the Ethernet controller checks for various error...

Page 658: ...A and the designated PAUSE DA 01 80 C2 00 00 01 If the receive block determines the received frame is a valid PAUSE frame the frame is rejected The receiver detects a PAUSE frame with the DA field set to the designated PAUSE DA or the unicast physical address If the DA is the individual unicast address the microcontroller performs an individual exact match comparison between the DA and 48 bit phys...

Page 659: ...ame False False False False True True True True Receive Frame Receive Frame Receive Frame Receive Frame Reject Frame Reject Frame Set BC bit in RCV BD Set MC bit in RCV BD if multicast Set M Miss bit in Rcv BD Set MC bit in Rcv BD if multicast Set BC bit in Rcv BD if broadcast Flush from FIFO Flush from FIFO Recognition Notes BC_REJ field in RCRn register BroadCast REJect PROM field in RCRn regist...

Page 660: ... If the CRC generator selects a bit set in the hash table the frame is accepted otherwise it is rejected For example if eight group addresses are stored in the hash table and random group addresses are received the hash table prevents roughly 56 64 87 5 of the group address frames from reaching memory Those that do reach memory must be further filtered by the processor to determine if they truly c...

Page 661: ...2 2 35FF_FFFF_FFFF 0x3 3 B5FF_FFFF_FFFF 0x4 4 95FF_FFFF_FFFF 0x5 5 D5FF_FFFF_FFFF 0x6 6 F5FF_FFFF_FFFF 0x7 7 DBFF_FFFF_FFFF 0x8 8 FBFF_FFFF_FFFF 0x9 9 BBFF_FFFF_FFFF 0xA 10 8BFF_FFFF_FFFF 0xB 11 0BFF_FFFF_FFFF 0xC 12 3BFF_FFFF_FFFF 0xD 13 7BFF_FFFF_FFFF 0xE 14 5BFF_FFFF_FFFF 0xF 15 27FF_FFFF_FFFF 0x10 16 07FF_FFFF_FFFF 0x11 17 57FF_FFFF_FFFF 0x12 18 77FF_FFFF_FFFF 0x13 19 F7FF_FFFF_FFFF 0x14 20 C7...

Page 662: ...FF_FFFF 0x28 40 4FFF_FFFF_FFFF 0x29 41 1FFF_FFFF_FFFF 0x2A 42 3FFF_FFFF_FFFF 0x2B 43 BFFF_FFFF_FFFF 0x2C 44 9FFF_FFFF_FFFF 0x2D 45 DFFF_FFFF_FFFF 0x2E 46 EFFF_FFFF_FFFF 0x2F 47 93FF_FFFF_FFFF 0x30 48 B3FF_FFFF_FFFF 0x31 49 F3FF_FFFF_FFFF 0x32 50 D3FF_FFFF_FFFF 0x33 51 53FF_FFFF_FFFF 0x34 52 73FF_FFFF_FFFF 0x35 53 23FF_FFFF_FFFF 0x36 54 13FF_FFFF_FFFF 0x37 55 3DFF_FFFF_FFFF 0x38 56 0DFF_FFFF_FFFF 0...

Page 663: ... timer uses the transmit backoff timer hardware for tracking the appropriate collision backoff time in half duplex mode The pause timer increments once every slot time until OPDn PAUSE_DUR slot times have expired On OPDn PAUSE_DUR expiration TCRn GTS is cleared allowing MAC data frame transmission to resume The receive flow control pause status bit TCRn RFC_PAUSE is set while the transmitter pause...

Page 664: ...e a JAM pattern is sent after the end of the preamble sequence If a collision occurs within 512 bit times one slot time the retry process is initiated The transmitter waits a random number of slot times If a collision occurs after 512 bit times then no retransmission is performed and the end of frame buffer is closed with a Late Collision LC error indication 26 5 14 MII Internal and External Loopb...

Page 665: ... clear RCR RMII_LOOP LOOP Figure 26 30 RMII Echo Mode 26 5 17 Ethernet Error Managing Procedure The Ethernet controller reports frame reception and transmission error conditions using the MIB block counters the FEC RxBDs and the EIRn register 26 5 17 1 Transmission Errors 26 5 17 1 1 Transmitter Underrun If this error occurs the FEC sends 32 bits that ensure a CRC error and stops transmitting All ...

Page 666: ...ition If TCRn HBC is set and the heartbeat condition is not detected by the FEC after a frame transmission a heartbeat error occurs When this error occurs the FEC closes the buffer sets EIRn HB and generates the HBERR interrupt if it is enabled 26 5 17 2 Reception Errors 26 5 17 2 1 Overrun Error If the receive block has data to put into the receive FIFO and the receive FIFO is full FEC sets RxBDn...

Page 667: ...Fast Ethernet Controllers FEC0 and FEC1 26 49 Freescale Semiconductor 26 5 17 2 5 Truncation When the receive frame length exceeds 2047 bytes frame is truncated and RxBDn TR is set ...

Page 668: ...in Figure 27 1 consists of separate transmit and receive circuits with FIFO registers and separate serial clock and frame sync generation for the transmit and receive sections The second set of Tx and Rx FIFOs replicates the logic used for the first set of FIFOs NOTE This device contains SSI bits to control the clock rate and the SSI DMA request sources within the chip configuration module CCM See...

Page 669: ... that implement the inter IC sound bus I2 S and the Intel AC97 standards Transmit Shift Reg 32 TXFIFO0 15x32 TXSR Internal Bus RXFIFO0 15x32 Receive Shift Reg SSI_RX0 RXSR Tx Clock Generator Tx Sync Generator Tx Control and State Machines Rx Clock Generator Rx Sync Generator Tx0 Data Reg SSI_TX0 Rx0 Data Reg Rx Control and State Machines TXFIFO1 15x32 Tx1 Data Reg SSI_TX1 RXFIFO1 15x32 SSI_RX1 Rx1...

Page 670: ...its which can be used in network mode to provide two independent channels for transmission and reception Programmable data interface modes such as I2 S lsb msb aligned Programmable word length 8 10 12 16 18 20 22 or 24 bits Program options for frame sync and clock generation Programmable I2 S modes master or slave Oversampling clock available as output from SSI_MCLK in I2 S master mode AC97 suppor...

Page 671: ...ec Both modes use the concept of a frame The beginning of the frame is marked with a frame sync when programmed with continuous clock The SSI_CCR DC bits determine length of the frame depending on whether data is being transmitted or received The number of words transferred per frame depends on the mode of the SSI In normal mode one data word transfers per frame In network mode the frame divides i...

Page 672: ... master mode this signal is referred to as the oversampling clock The frequency of SSI_MCLK is a multiple of the frame clock 27 2 4 SSI_FS Serial Frame Sync The input or output frame sync is used by the transmitter and receiver to synchronize the transfer of data The frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfer of...

Page 673: ... Figure 27 2 Synchronous SSI Configurations Continuous and Gated Clock Figure 27 3 shows an example of the port signals for an 8 bit data transfer Continuous and gated clock signals are shown as well as the bit length frame sync signal and the word length frame sync signal The shift direction can be defined as msb first or lsb first and there are other options on the clock and frame sync SSI Inter...

Page 674: ...lock out FS out 1 1 0 x Gated clock in 1 1 1 x Gated clock out Table 27 4 SSI Memory Map Address Register Width bits Access Reset Value Section Page 0xFC0B_C000 SSI Transmit Data Register 0 SSI_TX0 32 R W 0x0000_0000 27 3 1 27 8 0xFC0B_C004 SSI Transmit Data Register 1 SSI_TX1 32 R W 0x0000_0000 27 3 1 27 8 0xFC0B_C008 SSI Receive Data Register 0 SSI_RX0 32 R 0x0000_0000 27 3 4 27 10 0xFC0B_C00C S...

Page 675: ...ess 0xFC0B_C000 SSI_TX0 0xFC0B_C004 SSI_TX1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SSI_TX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27 4 SSI Transmit Data Registers SSI_TX0 SSI_TX1 Table 27 5 SSI_TX0 1 Field Descriptions Field Description 31 0 SSI_TX SSI transmit data The SSI_TX0 1 register...

Page 676: ...ifts data out to the SSI_TXD port The word length control bits SSI_CCR WL determine the number of bits to shift out of the TXSR before it is considered empty and can be written to again The data to be transmitted occupies the most significant portion of the shift register if SSI_TCR TXBIT0 is cleared Otherwise it occupies the least significant portion The unused portion of the register is ignored ...

Page 677: ...SI Receive Data Registers 0 and 1 SSI_RX0 1 The SSI_RX0 1 registers store the data received by the SSI For details on data alignment see Section 27 3 6 SSI Receive Shift Register RXSR SSI_TX 31 0 31 0 TXSR 12 bits 20 bits 24 bits 24 bits 12 bits 20 bits 16 bits 15 11 7 15 11 7 16 bits SSI_TXD SSI_TX 23 0 24 bits 11 12 bits 20 bits 16 bits 23 0 TXSR 11 15 19 15 19 31 SSI_TXD SSI_TX 23 0 15 TXSR 11 ...

Page 678: ... Data is transferred to the appropriate SSI receive data register or receive FIFOs if the receive FIFO is enabled and the corresponding SSI_RX is full after a word has been shifted in For receiving less than 24 bits of data the lsb bits are appended with 0 The following figures show the receiver loading and shifting operation They illustrate some possible values for WL which can be extended for th...

Page 679: ... msb Alignment Figure 27 12 Receive Data Path RXBIT0 1 RSHFD 0 lsb Alignment SSI_RX 31 0 12 bits 24 bits 20 bits 31 0 RXSR 24 bits 12 bits 20 bits 16 bits 7 11 15 7 11 15 16 bits SSI_RXD SSI_RX 31 0 31 0 24 bits 12 bits 20 bits 16 bits RXSR 7 11 15 7 11 15 16 bits 12 bits SSI_RXD 0 24 bits 11 RXSR 15 19 23 24 bits 12 bits 20 bits 16 bits 23 0 11 15 19 31 SSI_RX 31 SSI_RXD ...

Page 680: ...cleared 9 CIS Clock idle state Controls the idle state of the transmit clock port SSI_BCLK and SSI_MCLK during internal gated clock mode 0 Clock idle state is 1 1 Clock idle state is 0 8 TCH Two channel operation enable In this mode two time slots are used out of the possible 32 Any two time slots 0 31 can be selected by the mask registers The data in the two time slots is alternately handled by t...

Page 681: ...nues without interruption 0 Receiver disabled 1 Receiver enabled 1 TE Transmitter Enables the transfer of the contents of the SSI_TX registers to the TXSR and also enables the internal transmit clock The transmit section is enabled when this bit is set and a frame boundary is detected When this bit is cleared the transmitter continues to send data until the end of the current frame and then stops ...

Page 682: ...TUE0 TFS RFS TLS RLS RFF1 RFF0 TFE1 TFE0 W Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 Figure 27 15 SSI Interrupt Status Register SSI_ISR Table 27 8 SSI_ISR Field Descriptions Field Description 31 19 Reserved must be cleared 18 CMDAU AC97 command address register updated This bit causes the command address updated interrupt when the SSI_IER CMDAU bit is set This status bit is set each time there is a di...

Page 683: ...pt Required conditions Trigger Enabled SSI_IER RIE set SSI_IER RFF1 set SSI_ISR RFF1 sets Disabled SSI_IER RIE set SSI_IER RDR1 set SSI_RX1 loaded with new value Rx FIFO1 RDR1 is set when RDR1 is cleared during any of the following Enabled Rx FIFO1 loaded with new value Rx FIFO1 is empty SSI reset POR reset Disabled SSI_RX1 loaded with new value SSI_RX1 is read SSI reset POR reset Tx FIFO1 Transmi...

Page 684: ...d in two channel mode When a transmit underrun error occurs the previous data is retransmitted In network mode each time slot requires data transmission unless masked through the SSI_TMASK register when the transmitter is enabled Table 27 8 SSI_ISR Field Descriptions continued Field Description Rx FIFO1 Receiver overrun error 1 interrupt Required conditions Trigger Enabled SSI_IER RIE set SSI_IER ...

Page 685: ... Indicates occurrence of a receive frame sync during reception of the next word in SSI_RX registers Table 27 8 SSI_ISR Field Descriptions continued Field Description SSI Mode Transmit frame sync interrupt Required conditions Trigger Normal SSI_IER TIE set SSI_IER TFS set SSI_ISR TFS sets Network SSI Mode TFS is set when TFS is cleared when any of the following occur Normal TFS is always set SSI re...

Page 686: ...is full Table 27 8 SSI_ISR Field Descriptions continued Field Description Last time slot interrupts Required conditions Trigger TLS SSI_IER TIE set SSI_IER TLS set SSI_ISR TLS sets RLS SSI_IER RIE set SSI_IER RLS set SSI_ISR RLS sets Is set when Is cleared when any of the following occur TLS Start of last transmit time slot SSI_ISR is read with TLS set SSI reset POR reset RLS End of last receive t...

Page 687: ...6 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 RDMAE RIE TDMAE TIE CMD AU CMDU RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RDR1 RDR0 TDE1 TDE0 ROE1 ROE0 TUE1 TUE0 TFS RFS TLS RLS RFF1 RFF0 TFE1 TFE0 W Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 Figure 27 16 SSI Interrupt Enable Register SSI_IER Table 27 8 SSI_ISR Field Descriptions continued Field Description...

Page 688: ... FIFO is enabled a DMA request generates when either of the SSI_ISR TFE0 1 bits is set If the Tx FIFO is disabled a DMA request generates when either of the SSI_ISR TDE0 1 bits is set 0 SSI transmitter DMA requests disabled 1 SSI transmitter DMA requests enabled 19 TIE Transmit interrupt enable Allows the SSI to issue transmitter data related interrupts to the core Refer to Section 27 4 6 Transmit...

Page 689: ...ion Controls the direction and source of the clock signal on the SSI_BCLK pin Refer to Table 27 3 for details of clock port configuration 0 Clock is external 1 Clock generated internally 4 TSHFD Transmit shift direction Controls whether the msb or lsb is transmitted first in a sample 0 Data transmitted msb first 1 Data transmitted lsb first 3 TSCKP Transmit clock polarity Controls which bit clock ...

Page 690: ...gnment Allows SSI to receive the data word at bit position 0 or 15 31 in the receive shift register The shifting data direction can be msb or lsb first controlled by the RSHFD bit 0 msb aligned Shifting with respect to bit 31 if word length equals 16 18 20 22 or 24 or bit 15 if word length equals 8 10 or 12 of the receive shift register 1 lsb aligned Shifting with respect to bit 0 of the receive s...

Page 691: ...ame sync is one bit clock period long 0 REFS Receive early frame sync Controls when the frame sync is initiated for the receive section The frame sync is disabled after one bit for bit length frame sync and after one word for word length frame sync 0 Receive frame sync initiated as the first bit of data is received 1 Receive frame sync is initiated one bit before the data is received Address 0xFC0...

Page 692: ...e dividers The divide ratio works on the word clock In normal mode the ratio determines the word transfer rate Ranges from 1 to 32 In network mode this field sets the number of words per frame Ranges from 2 to 32 In normal mode a divide ratio of 1 DC 00000 provides continuous periodic data word transfer A bit length frame sync must be used in this case otherwise in word length mode the frame sync ...

Page 693: ...e 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R RFCNT1 3 0 TFCNT1 3 0 RFWM1 3 0 TFWM1 3 0 W RESET 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RFCNT0 3 0 TFCNT0 3 0 RFWM0 3 0 TFWM0 3 0 W RESET 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 Figure 27 20 SSI FIFO Control Status Register ...

Page 694: ...it Description Bits Description 0000 0 data word in receive FIFO 0001 1 data word in receive FIFO 0010 2 data word in receive FIFO 0011 3 data word in receive FIFO 0100 4 data word in receive FIFO 0101 5 data word in receive FIFO 0110 6 data word in receive FIFO 0111 7 data word in receive FIFO 1000 8 data word in receive FIFO 1001 9 data word in receive FIFO 1010 10 data word in receive FIFO 1011...

Page 695: ... Description Bits Description 0000 0 data word in transmit FIFO 0001 1 data word in transmit FIFO 0010 2 data word in transmit FIFO 0011 3 data word in transmit FIFO 0100 4 data word in transmit FIFO 0101 5 data word in transmit FIFO 0110 6 data word in transmit FIFO 0111 7 data word in transmit FIFO 1000 8 data word in transmit FIFO 1001 9 data word in transmit FIFO 1010 10 data word in transmit ...

Page 696: ...o the Receive FIFO Set when RxFIFO 5 6 15 data words 0110 RFF set when more than or equal to 6 data word have been written to the Receive Set when RxFIFO 6 7 15 data words 0111 RFF set when more than or equal to 7 data word have been written to the Receive FIFO Set when RxFIFO 7 8 15 data words 1000 RFF set when more than or equal to 8 data word have been written to the Receive FIFO Set when RxFIF...

Page 697: ...lots in Transmit FIFO Transmit FIFO empty is set when TxFIFO 10 data 0110 TFE set when there are more than or equal to 6 empty slots in Transmit FIFO Transmit FIFO empty is set when TxFIFO 9 data 0111 TFE set when there are more than or equal to 7 empty slots in Transmit FIFO Transmit FIFO empty is set when TxFIFO 8 data 1000 TFE set when there are more than or equal to 8 empty slots in Transmit F...

Page 698: ...ngs for receive FIFO watermark bits 3 0 TFWM0 3 0 Transmit FIFO Empty WaterMark 0 These bits control the threshold at which the TFE0 flag will be set The TFE0 flag is set whenever the empty slots in Tx FIFO exceed or are equal to the selected threshold Refer to Table 27 17 for details regarding settings for transmit FIFO watermark bits Table 27 18 Status of Transmit FIFO Empty Flag Transmit FIFO W...

Page 699: ...ame carries an AC97 write command or not When this bit is set the corresponding tag bits corresponding to command address and command data slots of the next transmit frame are automatically set The SSI automatically clears this bit after completing transmission of a frame 0 Next frame does not have a write command 1 Next frame does have a write command Note Do not set WR and RD at the same time 3 ...

Page 700: ...dance with the SSI_ACR WR and RD bits A direct write from the core or the information received in the incoming command address slot can update these bits If contents of these bits change due to an update the SSI_ISR CMDAU bit is set Address 0xFC0B_C040 SSI_ACDAT Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 AC...

Page 701: ...s register also generate the transmit tag in AC97 variable mode When the received tag value changes the SSI_ISR RXT bit is set if enabled If the SSI_ACR TIF bit is set the TAG value is also stored in Rx FIFO Note Bits 1 0 convey the codec ID Because only primary codecs are supported these bits must be cleared Address 0xFC0B_C048 SSI_TMASK Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 ...

Page 702: ... one time slot per frame data transfers only in the first time slot of the frame No data transfers in subsequent time slots In normal mode DC values corresponding to more than a single time slot in a frame only result in lengthening the frame 27 4 1 1 1 Normal Mode Transmit Conditions for data transmission from the SSI in normal mode are 1 SSI enabled SSI_CR SSI_EN 1 2 Enable FIFO and configure tr...

Page 703: ...rame sync active for continuous clock case 5 Bit clock begins for gated clock case With the above conditions in normal mode with a continuous clock each time the frame sync signal is generated or detected a data word is clocked in With the above conditions and a gated clock each time the clock begins a data word is clocked in If receive FIFO 0 is not enabled the received data word is transferred f...

Page 704: ...gister is loaded with the data to be transmitted On arrival of the clock this data transfers to the transmit shift register and transmits on the SSI_TXD output Simultaneously the receive shift register shifts in the received data available on the SSI_RXD input and at the end of the time slot this data transfers to the Rx data register In internal gated clock mode the Tx data line and clock output ...

Page 705: ...ch time slot is identified with respect to the frame sync data word time This time slot identification allows the option of transmitting data during the time slot by writing to the SSI_TX registers or ignoring the time slot as determined by the SSI_TMASK register bits The receiver is treated in the same manner and received data is only transferred to the receive data register FIFO if the correspon...

Page 706: ...ime slot Failing to reload the SSI_TX register before the TXSR is finished shifting empty causes a transmitter underrun error the TUE bit is set If the FIFO is enabled the TFE flag is set in accordance with the watermark setting and this flag causes a transmitter interrupt to occur Clearing the TE bit disables the transmitter after completion of transmission of the current frame Setting the TE bit...

Page 707: ...c external to the SSI e g GPIO can be reconfigured In two channel operation both the channels data registers FIFOs interrupts and DMA requests operate in the same manner as described above The only difference is second channel interrupts are generated only in this mode of operation Figure 27 30 shows the transmitter and receiver timing for an 8 bit word with continuous clock FIFO disabled three wo...

Page 708: ...ices In gated clock mode presence of the clock indicates that valid data is on the SSI_TXD or SSI_RXD signals For this reason no frame sync is needed in this mode After transmission of data completes the clock is pulled to the inactive state Gated clocks are allowed for the transmit and receive TX DATA TDE TUE RX DATA RDR ROE 0x5E 0x5E 0x5E 0xD6 0xD6 0x55 0x5E 0x55 0xD6 0x5E 0x3 0x7B 0x7B ZZ ZZ 0x...

Page 709: ...hould be taken to clear all DC bits when the module is used in gated mode For gated clock operated in external clock mode proper clock signalling must apply to SSI_BCLK for it to function properly If the SSI uses rising edge transition to clock data TSCKP 0 and falling edge transition to latch data RSCKP 0 the clock must be in an active low state when idle If the SSI uses falling edge transition t...

Page 710: ...The SSI is compliant to I2 S bus specification from Philips Semiconductors February 1986 Revised June 5 1996 Figure 27 35 depicts basic I2 S protocol timing Figure 27 35 I2 S Mode Timing Serial Clock Frame Sync and Serial Data I2 S mode can be selected by the SSI_CR I2S bits as follows In normal non I2S mode operation no register bits are forced to any particular state internally and the user can ...

Page 711: ...automatically performs these settings when in I2 S master mode Network mode is selected SSI_CR NET 1 Tx frame sync length set to one word long frame SSI_TCR TFSL 0 Rx frame sync length set to one word long frame SSI_RCR RFSL 0 Tx shifting w r t bit 0 of TXSR SSI_TCR TXBIT0 1 Rx shifting w r t bit 0 of RXSR SSI_RCR RXBIT0 1 Set the SSI_CCR PM PSR DIV2 WL DC control bits to configure the bit clock a...

Page 712: ...frame and the rest of the slots in that frame are all 20 bits wide The same sequence is followed while receiving data Refer to the AC97 specification for details regarding transmit and receive sequences and data formats NOTE Since the SSI has only one RxDATA pin only one codec is supported Secondary codecs are not supported When AC97 mode is enabled the hardware internally overrides the following ...

Page 713: ...slots 1 and 2 are always 20 bits wide 2 Select the number of time slots through the SSI_CCR DC bits For AC97 operation the DC bits should be set to a value of 0xC resulting in 13 time slots per frame 3 Write data to be transmitted in Tx FIFO 0 through Tx data register 0 4 Program the SSI_ACR FV TIF RD WR and FRDIV bits 5 Update the contents of SSI_ACADD SSI_ACDAT and SSI_ATAG for fixed mode only r...

Page 714: ...the user to operate the SSI module at frequencies that would not be achievable if standard internal core clock frequencies are used This is also the output master clock SSI_MCLK when in master mode Bit clock Serially clocks the data bits in and out of the SSI port This clock is generated internally or taken from external clock source through SSI_BCLK Word clock Counts the number of data bits per w...

Page 715: ...rate clock generation A programmable frame rate divider and a word length divider are used for frame rate sync signal generation Figure 27 37 shows a block diagram of the clock generator for the transmit section The serial bit clock can be internal or external depending on the transmit direction SSI_TCR TXDIR bit Figure 27 37 SSI Transmit Clock Generator Block Diagram Figure 27 38 shows the frame ...

Page 716: ...z In the next example SSI_CLOCK is 12 MHz A 16 bit word network mode with DC 1 PM 1 the PSR 0 DIV2 1 a bit clock rate of 12 14 2 1 5 MHz is generated Because the 16 bit word rate equals two sampling rate or frame sync rate would be 1 5 2 16 46 875 kHz Table 27 26 shows the example of programming PSR and PM bits to generate different bit clock SSI_BCLK frequencies The SSI_CLKIN signal is used in th...

Page 717: ... should be synchronized with the rising edge of external clock signal SSI_BCLK 27 4 4 Supported Data Alignment Formats The SSI supports three data formats to provide flexibility with managing data These formats dictate how data is written to and read from the data registers Therefore data can appear in different places in SSI_TX0 1 and SSI_RX0 1 based on the data format and the number of bits per ...

Page 718: ...bit This format is useful when data is stored in a fixed point integer format which implies fractional values Table 27 28 Data Alignment Format Bit Number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 bit lsb Aligned 7 6 5 4 3 2 1 0 8 bit msb Aligned 7 6 5 4 3 2 1 0 10 bit lsb Aligned 9 8 7 6 5 4 3 2 1 0 10 bit msb Aligned 9 8 7 6 5 4 3 2 1 0 12 bit lsb Al...

Page 719: ...ata register full condition Reading the SSI_RX registers clears the RDR bits thus clearing the pending interrupt Two receive data interrupts two per channel in two channel mode are available receive data with exception status and receive data without exception Table 27 29 shows the conditions these interrupts are generated 27 4 6 Transmit Interrupt Enable Bit Description The SSI transmit interrupt...

Page 720: ...n reset The SSI control bits including those in SSI_CR are unaffected The SSI reset is useful for selective reset of the SSI without changing the present SSI control bits and without affecting the other peripherals The correct sequence to initialize the SSI is 1 Issue a power on or SSI reset SSI_CR SSI_EN 0 2 Set all control bits for configuring the SSI refer to Table 27 31 3 Enable appropriate in...

Page 721: ...ore Change Control Register Bit SSI_CR 9 CIS 8 TCH 7 MCE 6 5 I2S 4 SYN 3 NET SSI_IER 22 RDMAE 20 TDMAE SSI_RCR SSI_TCR 9 RXBIT0 and TXBIT0 8 RFEN1 and TFEN1 7 RFEN0 and TFEN0 6 TFDIR 5 RXDIR and TXDIR 4 RSHFD and TSHFD 3 RSCKP and TSCKP 2 RFSI and TFSI 1 RFSL and TFSL 0 REFS and TEFS SSI_CCR 16 13 WL SSI_ACR 1 FV 10 5 FRDIV ...

Page 722: ...ram 28 1 1 Overview This section discusses how to operate and program the real time clock RTC module that maintains a time of day clock provides stopwatch alarm and interrupt functions and supports the following features Clock Sampling Second Minute Hour Day Interrupt Control To Interrupt Controller Clock Control Interrupt Enable Interrupt Status To Internal 1pps 1 ppm 1 pph 1 ppd Time of Day Cloc...

Page 723: ...three registers RTC_SECONDS contains the 6 bit seconds counter RTC_HOURMIN contains the 6 bit minutes counter and 5 bit hours counter RTC_DAYS contains the 16 bit day counter Alarm There are three alarm registers that mirror the three counter registers An alarm is set by accessing the real time clock alarm registers RTC_ALRM_SEC RTC_ALRM_HM and RTC_ALRM_DAY and loading the time minus one second th...

Page 724: ...ss Register Width bits Access Reset Value Section Page 0xFC03_C000 RTC Hours and Minutes Counter Register RTC_HOURMIN 32 R W Undefined 28 3 1 28 3 0xFC03_C004 RTC Seconds Counter Register RTC_SECONDS 32 R W Undefined 28 3 2 28 4 0xFC03_C008 RTC Hours and Minutes Alarm Register RTC_ALRM_HM 32 R W 0x0000_0000 28 3 3 28 4 0xFC03_C00C RTC Seconds Alarm Register RTC_ALRM_SEC 32 R W 0x0000_0000 28 3 4 2...

Page 725: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOURS 0 0 MINUTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 2 RTC Hours and Minutes Counter Register RTC_HOURMIN Table 28 3 RTC_HOURMIN Field Descriptions Field Description 31 13 Reserved must be cleared 12 8 HOURS Current hour Set to any value between 0 and 23 0x17 7 6 Reserved must be cleared 5 0 MINUTES Current minutes Set to any value between...

Page 726: ...8 4 RTC Hours and Minutes Alarm Register RTC_ALRM_HM Table 28 5 RTC_ALRM_HM Field Descriptions Field Description 31 13 Reserved must be cleared 12 8 HOURS Hours setting of the alarm Set to any value between 0 and 23 0x17 7 6 Reserved must be cleared 5 0 MINUTES Minutes setting of the alarm Set to any value between 0 and 59 0x3B Address 0xFC03_C00C RTC_ALRM_SEC Access User read write 31 30 29 28 27...

Page 727: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN 0 0 0 0 0 0 SWR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Figure 28 6 RTC Control Register RTC_CR Table 28 7 RTC_CR Field Descriptions Field Description 31 8 Reserved must be cleared 7 EN RTC enable Enables disables the real time clock module SWR has no effect on this bit 0 Disable the RTC 1 Enable the RTC 6 1 Reserved must be cleared 0...

Page 728: ...lag If enabled this bit is set on every increment of the hour counter in the RTC_HOURMIN register 0 No interrupt has occurred 1 An hour interrupt has occurred 4 1HZ 1 Hz interrupt flag If enabled this bit is set on every increment of the second counter of the RTC_SECONDS register 0 No interrupt has occurred 1 A 1 Hz interrupt has occurred 3 DAY Day interrupt flag If enabled this bit is set on ever...

Page 729: ...t disabled 1 SAM7 0 interrupt enabled 7 2HZ 2 Hz interrupt enable 0 Interrupt disabled 1 2 Hz interrupt enabled 6 Reserved must be cleared 5 HR Hour interrupt enable 0 Interrupt disabled 1 Hour interrupt enabled 4 1HZ 1 Hz interrupt enable 0 Interrupt disabled 1 1 Hz interrupt enabled 3 DAY Day interrupt enable 0 Interrupt disabled 1 Day interrupt enabled 2 ALM Alarm interrupt enable 0 Interrupt d...

Page 730: ... 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Figure 28 9 RTC Stopwatch Minutes Register RTC_STPWCH Table 28 10 RTC_STPWCH Field Descriptions Field Description 31 6 Reserved must be cleared 5 0 CNT Stopwatch count Contains the stopwatch countdown value plus one minute Stopwatch counter decrements by the ...

Page 731: ...5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAYS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 11 RTC Day Alarm Register RTC_ALRM_DAY Table 28 12 RTC_ALM_DAYS Field Descriptions Field Description 31 16 Reserved must be cleared 15 0 DAYS Current day setting of the alarm Set to any value between 0 and 65 535...

Page 732: ...sters The 6 bit seconds counter is located in RTC_SECONDS The 6 bit minutes counter and the 5 bit hours counter are located in RTC_HOURMIN The 16 bit day counter is located in RTC_DAYS These counters cover a 24 hour clock over 65 536 days All three registers can be read or written at any time Interrupts signal when each of the four counters increments and can indicate when a counter rolls over For...

Page 733: ...ly if the real time clock is enabled and the 1 Hz signal is programmed to clock at 1 Hz The sample clock which is equal to SAM7 is generated by dividing the RTC oscillator frequency by the value programmed into RTC_GOC 31 9 which is equal to RTC_GOCU 15 0 RTC_GOCL 15 9 The following table lists example interrupt frequencies of the sampling timer for possible combinations of RTC oscillator frequenc...

Page 734: ...eprogrammed The actual delay includes the seconds from setting the stopwatch to the next minute tick 28 5 Initialization Application Information 28 5 1 Flow Chart of RTC Operation Table 28 14 shows the flow chart of a typical RTC operation Figure 28 14 Flow Chart of RTC Operation 28 5 2 Programming the Alarm or Time of Day Registers Use the following procedure illustrated in Figure 28 15 when chan...

Page 735: ... Flow Chart of Alarm and Time of Day Programming Clear any incidental alarm interrupt Enable the alarm interrupt Disable the alarm interrupt Program the alarm or time of day registers clear RTC_IER ALM write 1 to RTC_ISR ALM during programming set RTC_IER ALM ...

Page 736: ...or it can be a free running down counter 29 1 2 Block Diagram Figure 29 1 PIT Block Diagram 29 1 3 Low Power Mode Operation This subsection describes the operation of the PIT modules in low power modes and debug mode of operation Low power modes are described in the power management module Chapter 9 Power Management Table 29 1 shows the PIT module operation in low power modes and how it can exit f...

Page 737: ...de is exited the PIT continues to operate in its pre debug mode state but any updates made in debug mode remain 29 2 Memory Map Register Definition This section contains a memory map see Table 29 2 and describes the register structure for PIT0 PIT3 NOTE Longword accesses to any of the programmable interrupt timer registers results in a bus error Only byte and word accesses are allowed Table 29 1 P...

Page 738: ...to reserved address locations have no effect and result in a cycle termination transfer error 2 User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error Address 0xFC08_0000 PCSR0 0xFC08_4000 PCSR1 0xFC08_8000 PCSR2 0xFC08_C000 PCSR3 Access Supervisor read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 PRE 0 DOZE DBG OVW PIE PIF RLD EN W...

Page 739: ...g mode Reset clears DBG During debug mode register read and write accesses function normally When debug mode is exited timer operation continues from the state it was in before entering debug mode but any updates made in debug mode remain 0 PIT function not affected in debug mode 1 PIT function stopped in debug mode Note Changing the DBG bit from 1 to 0 during debug mode starts the PIT timer Likew...

Page 740: ...D Reload bit The read write reload bit enables loading the value of PMRn into PIT counter when the count reaches 0x0000 0 Counter rolls over to 0xFFFF on count of 0x0000 1 Counter reloaded from PMRn on count of 0x0000 0 EN PIT enable bit Enables PIT operation When PIT is disabled counter and prescaler are held in a stopped state This bit is read anytime write anytime 0 PIT disabled 1 PIT enabled A...

Page 741: ...m the Modulus Latch 29 3 2 Free Running Timer Operation This mode of operation is selected when the PCSRn RLD bit is clear In this mode the counter rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement When the counter reaches a count of 0x0000 PCSRn PIF flag is set If the PCSRn PIE bit is set PIF flag issues an interrupt request to the CPU Address 0x...

Page 742: ...s the internal bus clock period as selected by the PCSRn PRE bits The PMRn PM bits select the timeout period Eqn 29 1 29 3 4 Interrupt Operation Table 29 6 shows the interrupt request generated by the PIT The PIF flag is set when the PIT counter reaches 0x0000 The PIE bit enables the PIF flag to generate interrupt requests Clear PIF by writing a 1 to it or by writing to the PMR Table 29 6 PIT Inte...

Page 743: ... 1 1 Overview Each DMA timer module has a separate register set for configuration and control The timers can be configured to operate from the internal bus clock fsys or from an external clocking source using the DTnIN signal If the internal bus clock is selected it can be divided by 16 or 1 The selected clock source is routed to an 8 bit programmable prescaler that clocks the actual DMA timer cou...

Page 744: ... modes Programmable interrupt or DMA request on input capture or reference compare Ability to stop the timer from counting when the ColdFire core is halted DMA Timer Divider DMA Timer Mode Register DTMRn Prescaler Mode Bits DMA Timer Counter Register DTCNn 31 0 DMA Timer Reference Register DTRRn 31 0 DMA Timer Capture Register DTCRn 31 0 DMA Timer Event Register DTERn Capture Detection clock conta...

Page 745: ...xFC07_C002 DMA Timer n Extended Mode Register DTXMRn 8 R W 0x00 30 2 2 30 5 0xFC07_0003 0xFC07_4003 0xFC07_8003 0xFC07_C003 DMA Timer n Event Register DTERn 8 R W 0x00 30 2 3 30 5 0xFC07_0004 0xFC07_4004 0xFC07_8004 0xFC07_C004 DMA Timer n Reference Register DTRRn 32 R W 0xFFFF_FFFF 30 2 4 30 7 0xFC07_0008 0xFC07_4008 0xFC07_8008 0xFC07_C008 DMA Timer n Capture Register DTCRn 32 R W 0x0000_0000 30...

Page 746: ...does not affect DMA request or interrupt on capture function 1 Enable DMA request or interrupt upon reaching the reference value 3 FRR Free run restart 0 Free run Timer count continues incrementing after reaching the reference value 1 Restart Timer count is reset immediately after reaching the reference value 2 1 CLK Input clock source for the timer Avoid setting CLK when RST is already set Doing ...

Page 747: ...0 0xFC07_4002 DTXMR1 0xFC07_8002 DTXMR2 0xFC07_C002 DTXMR3 Access User read write 7 6 5 4 3 2 1 0 R DMAEN HALTED 0 0 0 0 0 MODE16 W Reset 0 0 0 0 0 0 0 0 Figure 30 3 DTXMRn Registers Table 30 3 DTXMRn Field Descriptions Field Description 7 DMAEN DMA request Enables DMA request output on counter reference match or capture edge event 0 DMA request disabled 1 DMA request enabled 6 HALTED Controls the...

Page 748: ...ure event The counter value has been latched into DTCRn Writing a 1 to CAP clears the event condition Writing a 0 has no effect REF DTMRn ORRI DTXMRn DMAEN 0 X X No event 1 0 0 No request asserted 1 0 1 No request asserted 1 1 0 Interrupt request asserted 1 1 1 DMA request asserted CAP DTMRn CE DTXMRn DMAEN 0 XX X No event 1 00 0 Disable capture event output 1 00 1 Disable capture event output 1 0...

Page 749: ... capture mode is used Address 0xFC07_0004 DTRR0 0xFC07_4004 DTRR1 0xFC07_8004 DTRR2 0xFC07_C004 DTRR3 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R REF 32 bit reference value W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 30 5 DTRRn Registers Table 30 5 DTRRn Field Descriptions Field Description 31 0 R...

Page 750: ...value when the corresponding input capture edge detector senses a defined DTnIN transition The capture edge bits DTMRn CE select the type of transition that triggers the capture and sets the timer event register capture event bit DTERn CAP If DTERn CAP and DTXMRn DMAEN are set a DMA request is asserted If DTERn CAP is set and DTXMRn DMAEN is cleared an interrupt is asserted 30 3 3 Reference Compar...

Page 751: ...outed to the prescaler Internal bus clock can be divided by 1 or 16 DTnIN the maximum value of DTnIN is 1 5 of the internal bus clock as described in the device s electrical characteristics NOTE DTnIN may not be configured as a clock source when the timer capture mode is selected or indeterminate operation results The 8 bit DTMRn PS prescaler value is set Using DTMRn RST counter is cleared and sta...

Page 752: ...ent flags move w TMR0 D0 save the contents of TMR0 while setting bset 0 D0 the 0 bit This enables timer 0 and starts counting move w D0 TMR0 load the value back into the register setting TMR0 RST T0_LOOP move b TER0 D1 load TER0 and see if btst 1 D1 TER0 REF has been set beq T0_LOOP addi l 1 D2 Increment D2 cmp l 5 D2 Did D2 reach 5 i e timer ref has timed beq T0_FINISH If so end timer0 example Ot...

Page 753: ...ale Semiconductor For example if a 133 MHz timer clock is divided by 16 DTMRn PS equals 0x7F and the timer is referenced at 0x1FB5B 129 883 decimal the time out period is Eqn 30 2 Timeout period 1 133 10 6 16 127 1 129883 1 2 00 seconds ...

Page 754: ...I Block Diagram 31 1 2 Overview The DMA serial peripheral interface DSPI block provides a synchronous serial bus for communication between an MCU and an external peripheral device The DSPI supports up to 32 queued SPI transfers 16 receive and 16 transmit in the DSPI resident FIFOs eliminating CPU intervention between transfers CMD DMA and Interrupt Control TX FIFO RX FIFO TX Data RX Data 16 16 Shi...

Page 755: ... updates to SPI queues Programmable transfer attributes on a per frame basis Eight clock and transfer attribute registers Serial clock with programmable polarity and phase Programmable delays PCS to SCK delay SCK to PCS delay Delay between frames Programmable serial frame size of 4 to 16 bits expandable with software control Continuously held chip select capability Five peripheral chip selects exp...

Page 756: ...nsfer attributes are controlled by the SPI command in the current TX FIFO entry The CTAS field in the SPI command selects which of the eight DSPI_CTARs sets the transfer attributes Transfer attribute control is on a frame by frame basis See Section 31 4 2 Serial Peripheral Interface SPI Configuration for more details 31 1 4 2 Slave Mode In slave mode the DSPI responds to transfers initiated by an ...

Page 757: ...signal is a slave select input signal allowing an SPI master to select the DSPI as the target for transmission 31 2 3 Peripheral Chip Selects 1 3 DSPI_PCS 1 3 The DSPI_PCS 1 3 signals are peripheral chip select output signals in master mode In slave mode these signals are not used 31 2 4 Peripheral Chip Select 5 Peripheral Chip Select Strobe DSPI_PCS5 PCSS When the DSPI is in master mode and the D...

Page 758: ...sociated with DSPI operation The HALT and MDIS bits can be changed at any time but only take effect on the next frame boundary Only the HALT and MDIS bits in the DSPI_MCR may be changed while the DSPI is running Table 31 2 DSPI Module Memory Map Address Register Width Access Reset Value Section Page 0xFC05_C000 DSPI module configuration register DSPI_MCR 32 R W 0x0000_4001 31 3 1 31 5 0xFC05_C008 ...

Page 759: ... bit is set Otherwise improper operation may occur 0 Slave mode 1 Master mode 30 CONT_ SCKE Continuous SCK enable Enables the serial communication clock DSPI_SCK to run continuously See Section 31 4 5 Continuous Serial Communications Clock for details 0 Continuous SCK disabled 1 Continuous SCK enabled 29 28 DCONF DSPI configuration Selects between the different configurations of the DSPI 00 SPI 01...

Page 760: ...able Allows the clock to be stopped to non memory mapped logic in DSPI effectively putting DSPI in a software controlled power saving state See Section 31 4 7 Power Saving Features for more information This bit is set at reset 0 Enable DSPI clocks 1 Allow external logic to disable DSPI clocks 13 DIS_TXF Disable transmit FIFO When the TX FIFO is disabled transmit part of the DSPI operates as a simp...

Page 761: ...1 Reserved must be cleared 0 HALT Halt Starts and stops DSPI transfers See Section 31 4 1 Start and Stop of DSPI Transfers for details on the operation of this bit 0 Start transfers 1 Stop transfers Address 0xFC05_C008 DSPI_TCR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SPI_TCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 ...

Page 762: ... the DSPI_CTAR0 registers sets the slave transfer attributes See the individual bit descriptions for details on which bits are used in slave modes Address 0xFC05_C00C DSPI_CTAR0 0xFC05_C010 DSPI_CTAR1 0xFC05_C014 DSPI_CTAR2 0xFC05_C018 DSPI_CTAR3 0xFC05_C01C DSPI_CTAR4 0xFC05_C020 DSPI_CTAR5 0xFC05_C024 DSPI_CTAR6 0xFC05_C028 DSPI_CTAR7 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 763: ...ate Generator for details on how to compute the baud rate If the overall baud rate is divided by two or three of the system clock the continuous SCK enable or the modified timing format enable bits must not be set 0 The baud rate is computed normally with a 50 50 duty cycle 1 Baud rate is doubled with the duty cycle depending on the baud rate prescaler 30 27 FMSZ Frame size Selects the number of b...

Page 764: ...dge of the DSPI_SCK This field is only used in master mode Note When the continuous selection format is selected CONT or DCONT is set switching the PCS to SCK delay prescaler without stopping the DSPI can cause errors in the transfer Note See Section 31 4 3 2 PCS to SCK Delay tCSC for details on calculating the PCS to SCK delay 00 1 clock DSPI_PCS to DSPI_SCK delay prescaler 01 3 clock DSPI_PCS to...

Page 765: ...15 12 CSSCK PCS to SCK delay scaler Selects the scaler value for the PCS to SCK delay This field is only used in master mode The PCS to SCK delay is the delay between the assertion of DSPI_PCS and the first edge of the DSPI_SCK The table below lists the scaler values Note When the continuous selection format is selected CONT or DCONT is set switching the PCS to SCK delay prescaler without stopping...

Page 766: ... time between the negation of the DSPI_PCS signal at the end of a frame and the assertion of DSPI_PCS at the beginning of the next frame The table below lists the scaler values Note See Section 31 4 3 4 Delay after Transfer tDT for more details on calculating the delay after transfer Table 31 5 DSPI_CTARn Field Description continued Field Description ASC After SCK Delay Scaler Value ASC After SCK ...

Page 767: ...I_SCK The table below lists the baud rate scaler values Note See Section 31 4 3 1 Baud Rate Generator for more details on calculating the baud rate Address 0xFC05_C02C DSPI_SR Access User Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R TCF TXRXS 0 EOQF TFUF 0 TFFF 0 0 0 0 0 RFOF 0 RFDF 0 W w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 768: ... The transmit underflow condition is detected only for DSPI modules operating in slave mode The TFUF bit is set when the TX FIFO of a DSPI operating in slave mode is empty and a transfer is initiated by an external SPI master The TFUF bit is cleared by writing 1 to it 0 TX FIFO underflow has not occurred 1 TX FIFO underflow has occurred 26 Reserved must be cleared 25 TFFF Transmit FIFO fill flag I...

Page 769: ...er of entries in the RX FIFO The RXCTR is decremented every time the DSPI_POPR is read The RXCTR is incremented after the last incoming databit is sampled but before the tASC delay starts Refer to Section 31 4 4 1 Classic SPI Transfer Format CPHA 0 for details 3 0 POPNXTPTR Pop next pointer Contains a pointer to the RX FIFO entry that is returned when the DSPI_POPR is read The POPNXTPTR is updated...

Page 770: ...d 24 TFFF_DIRS Transmit FIFO fill DMA or interrupt request select Selects between generating a DMA request or an interrupt request When the DSPI_SR TFFF flag bit and the DSPI_RSER TFFF_RE bit are set this bit selects between generating an interrupt request or a DMA request 0 TFFF flag generates interrupt requests 1 TFFF flag generates DMA requests 23 20 Reserved must be cleared 19 RFOF_RE Receive ...

Page 771: ...transfers 30 28 CTAS Clock and transfer attributes select Selects which of the DSPI_CTARn registers is used to set the transfer attributes for the associated SPI frame This field is used only in SPI master mode In SPI slave mode DSPI_CTAR0 is used instead 000 DSPI_CTAR0 001 DSPI_CTAR1 010 DSPI_CTAR2 011 DSPI_CTAR3 100 DSPI_CTAR4 101 DSPI_CTAR5 110 DSPI_CTAR6 111 DSPI_CTAR7 27 EOQ End of queue Prov...

Page 772: ...signals are asserted for the transfer This bit is used only in SPI master mode 0 Negate the DSPI_PCSn signal 1 Assert the DSPI_PCSn signal Note DSPI_PCS7 DSPI_PCS6 and DSPI_PCS4 are not implemented on this device Therefore these corresponding bits are reserved 15 0 TXDATA Transmit data Holds SPI data to be transferred according to the associated SPI command Note TXDATA is used in slave mode Addres...

Page 773: ... 0 0 0 0 0 0 0 Figure 31 9 DSPI Transmit FIFO Registers 0 15 DSPI_TXFRn Table 31 10 DSPI_TXFRn Field Descriptions Field Description 31 16 TXCMD Transmit command Contains the command that sets the transfer attributes for the SPI data See Section 31 3 6 DSPI Push Transmit FIFO Register DSPI_PUSHR for details on the command field 15 0 TXDATA Transmit data Contains the SPI data to be shifted out Addre...

Page 774: ...ow master and slave data is exchanged Figure 31 11 SPI Serial Protocol Overview The DSPI has five peripheral chip select DSPI_PCSn signals that select which of the slaves to communicate with Transfer protocols and timing properties are shared by the three DSPI configurations these properties are described independently of the configuration in Section 31 4 4 Transfer Formats The transfer rate and d...

Page 775: ...pt and DMA request conditions are described in Section 31 4 6 Interrupts DMA Requests The SPI configuration supports two module specific modes master mode and slave mode The FIFO operations are similar for both modes In master mode the DSPI initiates and controls the transfer according to the SPI command field of the TX FIFO entry In slave mode the DSPI only responds to transfers initiated by a bu...

Page 776: ...buffered simplified SPI when the FIFOs are disabled The FIFOs are disabled separately setting the DSPI_MCR DIS_TXF bit disables the TX FIFO and setting the DSPI_MCR DIS_RXF bit disables the RX FIFO The FIFO disable mechanisms are transparent to the user and to host software transmit data and commands are written to the DSPI_PUSHR and received data is read from the DSPI_POPR When the TX FIFO is dis...

Page 777: ...IFO The TX FIFO entries are removed drained by shifting SPI data out through the shift register Entries are transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the TX FIFO Every time an entry is transferred from the TX FIFO to the shift register the TX FIFO counter decrements by one At the end of a transfer the DSPI_SR TCF bit is set to indicate...

Page 778: ...eive FIFO Register DSPI_POPR A read of the DSPI_POPR decrements the RX FIFO counter by one Attempts to pop data from an empty RX FIFO are ignored and the RX FIFO counter remains unchanged The data returned from reading an empty RX FIFO is undetermined When the RX FIFO is not empty the RX FIFO drain flag DSPI_SR RFDF is set The RFDF bit is cleared when the RX_FIFO is empty and the eDMA controller i...

Page 779: ...tionship between these variables is given in the following Eqn 31 3 Table 31 15 shows an example of the computed after SCK delay 31 4 3 4 Delay after Transfer tDT The delay after transfer is the length of time between negation of DSPI_PCS signal for a frame and the assertion of DSPI_PCS signal for the next frame See Figure 31 15 for an illustration of the delay after transfer DSPI_CTARn PDT DT fie...

Page 780: ...ls and assertion of DSPI_PCSS is selected by the DSPI_CTARn PCSSCK field based on the following Eqn 31 5 At the end of transfer delay between DSPI_PCSS negation and DSPI_PCSn negation is selected by the DSPI_CTARn PASC field based on the following Eqn 31 6 Table 31 17 shows an example of the computed tPCSSCK delay Table 31 18 shows an example of the computed tPASC delay Table 31 16 Delay after Tra...

Page 781: ...he slave device to ensure proper transmission The DSPI supports four different transfer formats Classic SPI with CPHA 0 Classic SPI with CPHA 1 Modified transfer format with CPHA 0 Modified transfer format with CPHA 1 A modified transfer format is supported to allow for high speed communication with peripherals that require longer setup times The DSPI can sample the incoming data later than halfwa...

Page 782: ... At the next to last serial clock edge of the frame edge 15 of Figure 31 15 Master s TCF and EOQF are set and RXCTR counter is updated At the last serial clock edge of the frame edge 16 of Figure 31 15 Slave s TCF is set and RXCTR counter is updated 31 4 4 2 Classic SPI Transfer Format CPHA 1 The transfer format shown in Figure 31 16 communicates with peripheral SPI slave devices that require the ...

Page 783: ...TARn CPHA is set At the last serial clock edge edge 16 of Figure 31 16 Master s EOQF and TCF are set Slave s TCF is set Master s and slave s RXCTR counters are updated 31 4 4 3 Modified SPI Transfer Format MTFE 1 CPHA 0 In this modified transfer format the master and the slave sample later in the DSPI_SCK period than in classic SPI mode to allow for delays in device pads and board traces These del...

Page 784: ...ere the master samples the slave DSPI_SOUT Table 31 19 lists the number of system clock cycles between the active edge of DSPI_SCK and the master sample point for different values of the SMPL_PT bit field The master sample point can be delayed by one or two system clock cycles Figure 31 17 shows the modified transfer format for CPHA is cleared Only the condition where CPOL is cleared is illustrate...

Page 785: ...pling of the last bit The SCK to PCS delay must be greater or equal to half of the DSPI_SCK period NOTE For correct operation of the modified transfer format the user must thoroughly analyze the SPI link timing budget Figure 31 18 DSPI Modified Transfer Format MTFE 1 CPHA 1 Fsck Fsys 4 31 4 4 5 Continuous Selection Format Some peripherals must be deselected between every transfer Other peripherals...

Page 786: ...lf clock period The default settings for these provide a total of four system clocks In many situations tASC and tCSC must be increased if a full half clock period is required Switching DSPI_CTARn registers between frames while using continuous selection can cause errors in the transfer The DSPI_PCSn signal must be negated before DSPI_CTAR is switched When CONT is set and the DSPI_PCSn signals for...

Page 787: ...g CPHA is ignored if the CONT_SCKE bit is set Continuous SCK is supported for modified transfer format Clock and transfer attributes for the continuous SCK mode are set according to the following rules DSPI_CTAR0 is used initially At the start of each SPI frame transfer the DSPI_CTARn specified by the CTAS field for the frame is used The currently selected DSPI_CTARn remains in use until the start...

Page 788: ...equests The DSPI has six conditions that can only generate interrupt requests and two conditions that can generate an interrupt or DMA request Table 31 20 lists these conditions Table 31 20 Interrupt and DMA Request Conditions Condition Flag Interrupt DMA End of transfer queue has been reached EOQ EOQF X TX FIFO is not full TFFF X X Current frame transfer is complete TCF X TX FIFO underflow has oc...

Page 789: ...ble entries and the DSPI_RSER TFFF_RE bit is set The DSPI_RSER TFFF_DIRS bit selects whether a DMA request or an interrupt request is generated 31 4 6 3 Transfer Complete Interrupt Request TCF The transfer complete request indicates the end of the transfer of a serial frame The transfer complete request is generated at the end of each frame transfer when the DSPI_RSER TCF_RE bit is set See the TCF...

Page 790: ...ignals 31 4 7 Power Saving Features The DSPI supports two power saving strategies Module disable mode clock gating of non memory mapped logic Clock gating of slave interface signals and clock to memory mapped logic 31 4 7 1 Module Disable Mode Module disable mode is a mode the DSPI can enter to save power Host software can initiate the module disable mode by setting DSPI_MCR MDIS The MDIS bit is s...

Page 791: ...eceive queue by reading the DSPI_SR RXCNT bit or by checking the DSPI_SR RFDF bit after each read operation of the DSPI_POPR register 7 Modify DMA descriptor of TX and RX channels for new queues 8 Flush TX FIFO by writing a 1 to the DSPI_MCR CLR_TXF bit Flush RX FIFO by writing a 1 to the DSPI_MCR CLR_RXF bit 9 Clear transfer count by setting the CTCNT bit in the command word of the first entry in...

Page 792: ...CTARn PBR 2 3 5 7 Baud Rate Scaler Values DSPI_CTARn BR 2 25 0MHz 16 7MHz 10 0MHz 7 14MHz 4 12 5MHz 8 33MHz 5 00MHz 3 57MHz 6 8 33MHz 5 56MHz 3 33MHz 2 38MHz 8 6 25MHz 4 17MHz 2 50MHz 1 79MHz 16 3 12MHz 2 08MHz 1 25MHz 893kHz 32 1 56MHz 1 04MHz 625kHz 446kHz 64 781kHz 521kHz 312kHz 223kHz 128 391kHz 260kHz 156kHz 112kHz 256 195kHz 130kHz 78 1kHz 55 8kHz 512 97 7kHz 65 1kHz 39 1kHz 27 9kHz 1024 48 ...

Page 793: ... for the illustration but the concepts carry over to the RX FIFO See Section 31 4 2 4 TX FIFO Buffering Mechanism and Section 31 4 2 5 RX FIFO Buffering Mechanism for details on the FIFO operation Table 31 22 Delay Values Delay Prescaler Values DSPI_CTARn PBR 1 3 5 7 Delay Scaler Values DSPI_CTARn DT 2 20 0 ns 60 0 ns 100 0 ns 140 0 ns 4 40 0 ns 120 0 ns 200 0 ns 280 0 ns 8 80 0 ns 240 0 ns 400 0 ...

Page 794: ...X FIFO TXCTR TX FIFO counter TXNXTPTR transmit next pointer TX FIFO depth 16 31 5 5 2 Address Calculation for the First in and Last in Entries in the RX FIFO The memory address of the first in entry in the RX FIFO is computed by the following equation First in entry address RX FIFO base 4 POPNXTPTR The memory address of the last in entry in the RX FIFO is computed by the following equation Last in...

Page 795: ...minating the need for an external UART clock As Figure 32 1 shows each UART module interfaces directly to the CPU and consists of Serial communication channel Programmable clock generation Interrupt control logic and DMA request logic Internal channel control logic Figure 32 1 UART Block Diagram Serial Interrupt Control Logic Internal Channel Control Logic Programmable Clock Communications Channel...

Page 796: ...or use DMA requests for servicing See Section 32 4 2 2 Receiver NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins refer to Chapter 16 Pin Multiplexing and Control prior to configuring the UART module 32 1 2 Features The device contains three independent UART modules with Each clocked by external clock or internal bus clock eliminates need for an exte...

Page 797: ...n an interrupt request asserted to the CPU or a DMA request Table 32 1 UART Module External Signals Signal Description UnTXD Transmitter Serial Data Output UnTXD is held high mark condition when the transmitter is disabled idle or operating in the local loopback mode Data is shifted out on UnTXD on the falling edge of the clock source with the least significant bit lsb sent first UnRXD Receiver Se...

Page 798: ... 32 3 7 32 12 0xFC06_0010 0xFC06_4010 0xFC06_8010 UART Input Port Change Register UIPCRn 8 R See Section 32 3 8 32 12 UART Auxiliary Control Register UACRn 8 W 0x00 32 3 9 32 13 0xFC06_0014 0xFC06_4014 0xFC06_8014 UART Interrupt Status Register UISRn 8 R 0x00 32 3 10 32 13 UART Interrupt Mask Register UIMRn 8 W 0x00 0xFC06_0018 0xFC06_4018 0xFC06_8018 UART Baud Rate Generator Register UBG1n 8 W2 2...

Page 799: ... disabled for both Transmitter RTS control is configured in UMR2n TXRTS 0 The receiver has no effect on UnRTS 1 When a valid start bit is received UnRTS is negated if the UART s FIFO is full UnRTS is reasserted when the FIFO has an empty position available 6 RXIRQ FFULL Receiver interrupt select 0 RXRDY is the source generating interrupt or DMA requests 1 FFULL is the source generating interrupt o...

Page 800: ...the number of data bits per character to be sent The values shown do not include start parity or stop bits 00 5 bits 01 6 bits 10 7 bits 11 8 bits Address 0xFC06_0000 UMR20 0xFC06_4000 UMR21 0xFC06_8000 UMR22 Access User read write1 7 6 5 4 3 2 1 0 R CM TXRTS TXCTS SB W Reset 0 0 0 0 0 0 0 0 1 After UMR1n is read or written the pointer points to UMR2n Figure 32 4 UART Mode Registers 2 UMR2n Table ...

Page 801: ... Enables clear to send operation The transmitter checks the state of UnCTS each time it is ready to send a character If UnCTS is asserted the character is sent if it is deasserted the signal UnTXD remains in the high state and transmission is delayed until UnCTS is asserted Changes in UnCTS as a character is being sent do not affect its transmission 3 0 SB Stop bit length control Selects length of...

Page 802: ...s 0x with parity or force parity the corresponding character in the FIFO was received with incorrect parity If UMR1n PM equals 11 multidrop PE stores the received address or data A D bit PE is valid only when RXRDY is set 4 OE Overrun error Indicates whether an overrun occurs 0 No overrun occurred 1 One or more characters in the received data stream have been lost OE is set upon receipt of a new c...

Page 803: ...s now full Any characters received when the FIFO is full are lost 0 RXRDY Receiver ready 0 The CPU has read the receive buffer and no characters remain in the FIFO after this read 1 One or more characters were received and are waiting in the receive buffer FIFO Address 0xFC06_0004 UCSR0 0xFC06_4004 UCSR1 0xFC06_8004 UCSR2 Access User write only 7 6 5 4 3 2 1 0 R W RCS TCS Reset See Note See Note N...

Page 804: ...d of RECEIVER DISABLE when reconfiguring the receiver 011 RESET TRANSMITTER Immediately disables the transmitter and clears USRn TXEMP TXRDY No other registers are altered Because it places the transmitter in a known state use this command instead of TRANSMITTER DISABLE when reconfiguring the transmitter 100 RESET ERROR STATUS Clears USRn RB FE PE OE Also used in block mode to clear all error bits...

Page 805: ...already enabled this command has no effect 10 TRANSMITTER DISABLE Terminates transmitter operation and clears USRn TXEMP TXRDY If a character is being sent when the transmitter is disabled transmission completes before the transmitter becomes inactive If the transmitter is already disabled the command has no effect 11 Reserved do not use Command Description 00 NO ACTION TAKEN Causes the receiver t...

Page 806: ...the UART s TXRDY is cleared and the transmitter is disabled have no effect on the transmit buffer Figure 32 9 shows UTBn TB contains the character in the transmit buffer 32 3 8 UART Input Port Change Registers UIPCRn The UIPCRs hold the current state and the change of state for UnCTS Address 0xFC06_000C URB0 0xFC06_400C URB1 0xFC06_800C URB2 Access User read only 7 6 5 4 3 2 1 0 R RB W Reset 1 1 1...

Page 807: ...Rn COS 1 A change of state longer than 25 50 s occurred on the UnCTS input UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected 3 1 Reserved 0 CTS Current state of clear to send Starting two serial clock periods after reset CTS reflects the state of UnCTS If UnCTS is detected asserted at that time COS is set which initiates an interrupt if UACRn IEC is ena...

Page 808: ...ange condition to report Section 32 3 5 UART Command Registers UCRn describes the RESET BREAK CHANGE INTERRUPT command 1 The receiver detected the beginning or end of a received break 1 FFULL RXRDY Status of FIFO or receiver depending on UMR1 FFULL RXRDY bit Duplicate of USRn FIFO and USRn RXRDY 0 TXRDY Transmitter ready This bit is the duplication of USRn TXRDY 0 The transmitter holding register ...

Page 809: ...ver are enabled UBG1n and UBG2n are write only and cannot be read by the CPU 32 3 12 UART Input Port Register UIPn The UIPn registers show the current state of the UnCTS input Address 0xFC06_0018 UBG10 0xFC06_4018 UBG11 0xFC06_8018 UBG12 Access User write only 7 6 5 4 3 2 1 0 R W Divider MSB Reset 0 0 0 0 0 0 0 0 Figure 32 13 UART Baud Rate Generator Registers UBG1n Address 0xFC06_001C UBG20 0xFC0...

Page 810: ...IPn Field Descriptions Field Description 7 1 Reserved 0 CTS Current state of clear to send The UnCTS value is latched and reflects the state of the input pin when UIPn is read Note This bit has the same function and value as UIPCRn CTS 0 The current state of the UnCTS input is logic 0 1 The current state of the UnCTS input is logic 1 Address 0xFC06_0038 UOP10 0xFC06_003C UOP00 0xFC06_4038 UOP11 0x...

Page 811: ...cking Source Diagram NOTE If DTnIN is a clocking source for the timer or UART that timer module cannot use DTnIN for timer input capture 32 4 1 2 Calculating Baud Rates The following sections describe how to calculate baud rates 32 4 1 2 1 Internal Bus Clock Baud Rates When the internal bus clock is the UART clocking source it goes through a divide by 32 prescaler and then passes through the 16 bi...

Page 812: ... UART sets USRn TXRDY The transmitter converts parallel data from the CPU to a serial bit stream on UnTXD It automatically sends a start bit followed by the programmed number of data bits an optional parity bit and the programmed number of stop bits The lsb is sent first Data is shifted from the transmitter output on the falling edge of the clock source After the stop bits are sent if no new chara...

Page 813: ... continuous low condition by issuing a SEND BREAK command transmitter ignores the state of UnCTS If the transmitter is programmed to automatically negate UnRTS when a message transmission completes UnRTS must be asserted manually before a message is sent In applications in which the transmitter is disabled after transmission is complete and UnRTS is appropriately programmed UnRTS is negated one bi...

Page 814: ...n the receiver holding register are cleared After the stop bit is detected receiver immediately looks for the next start bit However if a non zero character is received without a stop bit framing error and UnRXD remains low for one half of the bit period after the stop bit is sampled receiver operates as if a new start bit were detected Parity error framing error overrun error and received break c...

Page 815: ...hen at least one character is available to be read by the CPU A read of the receive buffer produces an output of data from the top of the FIFO After the read cycle the data at the top of the FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom of the FIFO The FIFO full status bit FFULL is set if all three positions are filled with data The R...

Page 816: ...t is detected and the FIFO is full The receiver asserts UnRTS when a FIFO position becomes available therefore connecting UnRTS to the UnCTS input of the transmitting device can prevent overrun errors NOTE The receiver continues reading characters in the FIFO if the receiver is disabled If the receiver is reset the FIFO UnRTS control all receiver status bits interrupts and DMA requests are reset N...

Page 817: ...ust be enabled but the receiver need not be 32 4 3 3 Remote Loopback Mode In remote loopback mode shown in Figure 32 23 the UART automatically transmits received data bit by bit on the UnTXD output The local CPU to transmitter link is disabled This mode is useful in testing receiver and transmitter operation of a remote UART For this mode transmitter uses the receiver clock Because the receiver is...

Page 818: ... character sent from the master station consists of a start bit a programmed number of data bits an address data A D bit flag and a programmed number of stop bits A D equals 1 indicates an address character A D equals 0 indicates a data character The polarity of A D is selected through UMR1n PT UMR1n should be programmed before enabling the transmitter and loading the corresponding data bits into ...

Page 819: ...eserved registers complete normally without an error termination but data is ignored 32 5 Initialization Application Information The software flowchart Figure 32 25 consists of UART module initialization These routines consist of SINIT and CHCHK See Sheet 1 p 32 28 and Sheet 2 p 32 29 Before SINIT is called at system initialization the calling routine allocates 2 words on the system FIFO On return...

Page 820: ... memory and writing it into the UART transmit buffer UTBn This allows the DMA channel to stream data from memory to the UART for transmission without processor intervention After the entire message has been moved into the UART the DMA would typically generate an end of data transfer interrupt request to the CPU The resulting interrupt service routine ISR could query the UART programming model to d...

Page 821: ...C 2 0 0b001 2 UIMRn Enable the desired interrupt sources 3 UACRn Initialize the input enable control IEC bit 4 UCSRn Select the receiver and transmitter clock Use timer as source if required 5 UMR1n a If preferred program operation of receiver ready to send RXRTS bit a Select receiver ready or FIFO full notification RXRDY FFULL bit b Select character or block error mode ERR bit c Select parity mod...

Page 822: ...nductor 32 28 Figure 32 25 UART Mode Programming Flowchart Sheet 1 of 5 Serial Module SINIT Initiate Channel Interrupts CHK1 Call CHCHK Save Channel Status Enable Any Errors Y N Enable Receiver Assert Request To Send SINITR Return ...

Page 823: ...5 CHCHK CHCHK Place Channel In Local Loopback Mode Enable Transmitter Clear Status Word TxCHK Is Transmitter Ready Y N SNDCHR RxCHK Send Character To Transmitter Has Character Been Received N Y A Waited Too Long N N Waited Too Long Y Y Set Transmitter Never ready Flag Set Receiver Never ready Flag B ...

Page 824: ...chart Sheet 3 of 5 A B B FRCHK Have Framing Error Set Framing Error Flag PRCHK Have Parity Error Set Parity Error Flag Get Character From Receiver Same As Transmitted Character Set Incorrect Character Flag N N Y CHRCHK Y N Disable Transmitter RSTCHN Restore To Original Mode Return Y ...

Page 825: ...A Break SIRQ ABRKI N Clear Change in Break Status Bit ABRKI1 N Has End of break IRQ Arrived Yet Y Y Clear Change in Break Status Bit Remove Break Character From Receiver FIFO Replace Return Address On System Stack And Monitor Warm Start Address SIRQR RTE N Y Does Channel A Receiver Have A Character INCH Place Character In D0 Return ...

Page 826: ...UART Modules Freescale Semiconductor 32 32 Figure 32 25 UART Mode Programming Flowchart Sheet 5 of 5 OUTCH Is Transmitter Ready N Y Send Character To Transmitter Return ...

Page 827: ...illustrating the interaction of the registers described in Section 33 2 Memory Map Register Definition Figure 33 1 I2 C Module Block Diagram Address Compare In Out Data Shift Start Stop Input Sync Clock Control Registers and Slave Interface Address Decode I2C Address Data MUX Address IRQ Data and Arbitration Control Register Internal Bus Register I2C Frequency Divider Register I2C Data I O Registe...

Page 828: ...ttempt to control the bus simultaneously This supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly line computer NOTE The I2 C module is compatible with the Philips I2 C bus protocol For information on system configuration protocol and restrictions see The I2 C Bus Specification Version...

Page 829: ...8000 I2 C Address Register I2ADR R W 0x00 33 2 1 33 3 0xFC05_8004 I2 C Frequency Divider Register I2FDR R W 0x00 33 2 2 33 3 0xFC05_8008 I2 C Control Register I2CR R W 0x00 33 2 3 33 4 0xFC05_800C I2 C Status Register I2SR R W 0x81 33 2 4 33 5 0xFC05_8010 I2 C Data I O Register I2DR R W 0x00 33 2 5 33 6 Address 0xFC05_8000 I2ADR Access User read write 7 6 5 4 3 2 1 0 R ADR 0 W Reset 0 0 0 0 0 0 0 ...

Page 830: ...ress 0xFC05_8008 I2CR Access User read write 7 6 5 4 3 2 1 0 R IEN IIEN MSTA MTX TXAK RSTA 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 33 4 I2 C Control Register I2CR IC Divider IC Divider IC Divider IC Divider 0x00 28 0x10 288 0x20 20 0x30 160 0x01 30 0x11 320 0x21 22 0x31 192 0x02 34 0x12 384 0x22 24 0x32 224 0x03 40 0x13 480 0x23 26 0x33 256 0x04 44 0x14 576 0x24 28 0x34 320 0x05 48 0x15 640 0x25 32 0x3...

Page 831: ...oses arbitration MSTA is cleared without generating a STOP signal 0 Slave mode Changing MSTA from 1 to 0 generates a STOP and selects slave mode 1 Master mode Changing MSTA from 0 to 1 signals a START on the bus and selects master mode 4 MTX Transmit receive mode select bit Selects the direction of master and slave transfers 0 Receive 1 Transmit When the device is addressed as a slave software mus...

Page 832: ...ess or data transmit cycle I2C_SDA sampled low when the master drives high during the acknowledge bit of a data receive cycle A start cycle is attempted when the bus is busy A repeated start cycle is requested in slave mode A stop condition is detected when the master did not request it 3 Reserved must be cleared 2 SRW Slave read write When IAAS is set SRW indicates the value of the R W command bi...

Page 833: ... beginning of a data transfer each data transfer can be several bytes long and awakens all slaves Address 0xFC05_8010 I2DR Access User read write 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 Figure 33 6 I2C Data I O Register I2DR Table 33 6 I2DR Field Description Field Description 7 0 DATA I2 C data When data is written to this register in master transmit mode a data transfer is initiated The mo...

Page 834: ...by the R W bit sent by the calling master Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high as Figure 33 7 shows I2C_SCL is pulsed once for each data bit with the msb being sent first The receiving device must acknowledge each byte by pulling I2C_SDA low at the ninth clock therefore a data byte transfer takes nine clock pulses See Figure 33 8 Figure 33 8 D...

Page 835: ... master to generate a STOP or START signal Figure 33 9 33 3 5 STOP Signal The master can terminate communication by generating a STOP signal to free the bus A STOP signal is defined as a low to high transition of I2C_SDA while I2C_SCL is at logical high see F in Figure 33 7 The master can generate a STOP even if the slave has generated an acknowledgment at which point the slave must release the bu...

Page 836: ...nt mode without releasing the bus The master transmits data to the slave first and then the master reads data from slave by reversing the R W bit Figure 33 11 Data Transfer Combined Format 1 2 3 4 5 6 7 8 1 2 5 6 7 8 3 4 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R W 9 9 XX New Calling Address R W No ACK Bit STOP Signal Repeated START Signal ACK Bit R W Calling Address START msb l...

Page 837: ...r a high wait state during this time see Figure 33 12 When all devices concerned have counted off their low period the synchronized clock I2C_SCL line is released and pulled high At this point the device clocks and the I2C_SCL line are synchronized and the devices start counting their high periods The first device to complete its high period pulls the I2C_SCL line low again Figure 33 12 Clock Sync...

Page 838: ...2 2 I2C Frequency Divider Register I2FDR 2 Update the I2ADR to define its slave address 3 Set I2CR IEN to enable the I2 C bus interface system 4 Modify the I2CR to select or deselect master slave mode transmit receive mode and interrupt enable or not NOTE If I2SR IBB is set when the I2 C bus module is enabled execute the following pseudocode sequence before proceeding with normal initialization co...

Page 839: ... the interrupt function is disabled Polling should monitor IIF rather than ICF because that operation is different when arbitration is lost When an interrupt occurs at the end of the address cycle the master is always in transmit mode the address is sent If master receive mode is required I2CR MTX should be toggled During slave mode address cycles I2SR IAAS 1 I2SR SRW is read to determine the dire...

Page 840: ... set is from the interrupt at the end of the address cycle where an address match occurred interrupts resulting from subsequent data transfers have IAAS cleared A data transfer can now be initiated by writing information to I2DR for slave transmits or read from I2DR in slave receive mode A dummy read of I2DR in slave receive mode releases I2C_SCL allowing the master to send data In the slave trans...

Page 841: ...R Generate STOP Signal Read Data from I2DR And Store Set TXAK 1 Generate STOP Signal 2nd Last Byte to be Last Byte to be Arbitration Lost Clear IAL IAAS 1 IAAS 1 SRW 1 Tx Rx Set TX Mode Write Data to I2DR Set RX Mode Dummy Read from I2DR ACK from Receiver Tx Next Byte Read Data from I2DR and Store Switch to Rx Mode Dummy Read from I2DR RTE Y N Y Y Y Y Y Y Y Y Y N N N N N N N N N Y TX RX RX TX WRIT...

Page 842: ...I2 C Interface Freescale Semiconductor 33 16 ...

Page 843: ...Freescale Semiconductor 1 ...

Page 844: ...ex is halted and a variety of commands can be sent to the processor to access memory registers and peripherals The external emulator uses a three pin serial full duplex channel See Section 34 4 1 Background Debug Mode BDM and Section 34 3 Memory Map Register Definition Real time debug support BDM requires the processor to be halted which many real time embedded applications cannot do Debug interru...

Page 845: ...tual address to include the 8 bit address space identifier ASID Conceptually the virtual address is expanded to a 40 bit value the 8 bit ASID plus the 32 bit address The expansion of the virtual address affects two major debug functions The ASID is optionally included in the specification of the hardware breakpoint registers As an example the four PC breakpoint registers are each expanded by 8 bit...

Page 846: ... for the RTS instruction D 0011 MMU enhancements to support ASID FORCE_TA command D 1011 Added CSR IPI for revision D Table 34 2 Debug Module Signals Signal Description Development Serial Clock DSCLK Internally synchronized input The logic level on DSCLK is validated if it has the same value on two consecutive rising bus clock edges Clocks the serial communication port to the debug module during p...

Page 847: ...r the example in Table 34 3 is shown in Figure 34 2 Processor Status Clock PSTCLK Half speed version of the processor clock Its rising edge appears in the center of the two processor cycle window of valid PSTDDATA output PSTCLK indicates when the development system should sample PSTDDATA values The following figure shows PSTCLK timing with respect to PSTDDATA If real time trace is not used setting...

Page 848: ...debug module contain a number of registers to support the required functionality These registers are also accessible from the processor s supervisor programming model by executing the WDEBUG instruction write only Therefore the breakpoint hardware in debug module can be read or written by the external development system using the debug serial interface or written by the operating Table 34 4 PSTDDA...

Page 849: ... 32 bit register reserved fields are not used don t care W 0x05 34 3 3 34 11 0x06 Address attribute trigger register AATR 32 W 0x0000_0005 34 3 4 34 12 0x07 Trigger definition register TDR 32 W 0x0000_0000 34 3 5 34 14 0x08 PC breakpoint register 0 PBR0 32 W Undefined 34 3 6 34 17 0x09 PC breakpoint mask register PBMR 32 W Undefined 34 3 6 34 17 0x0A PC breakpoint ASID control PBAC 32 W Undefined ...

Page 850: ... using the WDEBUG instruction Two ASID related registers PBAC and PBASID are added for the PC breakpoint qualification and two existing registers AATR and AATR1 are expanded for the address breakpoint qualification 34 3 1 Shared Debug Resources The debug module revision A implementation provides a common hardware structure for BDM and breakpoint functionality Certain hardware structures are used f...

Page 851: ...d Description 31 28 BSTAT Breakpoint Status Provides read only status from the BDM port only information concerning hardware breakpoints Also output on PSTDDATA when it is not displaying PST or other processor data BSTAT is cleared by a TDRor XTDR write or by a CSR read when a level 2 breakpoint is triggered or a level 1 breakpoint is triggered and the level 2 breakpoint is disabled 0000 No breakp...

Page 852: ...writes to the debug module s programming model registers Only commands from the external development system can modify IPW 15 MAP Force processor references in emulator mode 0 All emulator mode references are mapped into supervisor code and data spaces 1 The processor maps all references while in emulator mode to a special address space TT equals 10 TM equals 101 or 110 The internal SRAM and cache...

Page 853: ...recise An address or data breakpoint should always occur before the next instruction begins execution Therefore the occurrence of the address data breakpoints should be guaranteed 5 IPI Ignore pending interrupts 0 Core services any pending interrupt requests that were signalled while in single step mode 1 Core ignores any pending interrupt requests signalled while in single instruction step mode 4...

Page 854: ...ATRn is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the WDMREG command This register is expanded to include an optional ASID specification and a control bit that enables the use of the ASID field DRc 4 0 0x05 BAAR Access Supervisor write only BDM write only 7 6 5 4 3 2 1 0 R W R SZ TT TM Reset 0 0 0 0 0 1 0 1 Figure 34 4 ...

Page 855: ... the address breakpoint defined in ABLR ABHR and AATR 0 Disable ASID qualifier reset default 1 Enable ASID qualifier 23 16 AATRASID ABLR ABHR AATR ASID Corresponds to the ASID to be included in the address breakpoint specified by ABLR ABHR and AATR 15 RM Read write Mask Setting RM masks R in address comparisons 14 13 SZM Size Mask Setting an SZM bit masks the corresponding SZ bit in address compar...

Page 856: ...akpoint handler for the second level 1 breakpoint to occur 4 3 TT Transfer Type Compared with the local bus transfer type signals 00 Normal processor access 01 Reserved 10 Emulator mode access 11 These bits also define the TT encoding for BDM memory commands In this case the 01 encoding indicates an external or DMA access for backward compatibility These bits affect the TM bits 2 0 TM Transfer Mod...

Page 857: ...nes how the processor responds to a completed trigger condition The trigger response is always displayed on PSTDDATA 00 Display on PSTDDATA only 01 Processor halt 10 Debug interrupt 11 Reserved 29 L2EBL Enable Level 2 Breakpoint Global enable for the breakpoint trigger 0 Disables all level 2 breakpoints 1 Enables all level 2 breakpoint triggers 28 22 L2ED Enable Level 2 Data Breakpoint Setting an ...

Page 858: ...el 1 Breakpoint Global enable for the breakpoint trigger 0 Disables all level 1 breakpoints 1 Enables all level 1 breakpoint triggers 12 6 L1ED Enable Level 1 Data Breakpoint Setting an L1ED bit enables the corresponding data breakpoint condition based on the size and placement on the processor s local data bus Clearing all L1ED bits disables data breakpoints Table 34 10 TDR Field Descriptions con...

Page 859: ...ense of all the data breakpoint comparators This can develop a trigger based on the occurrence of a data value other than the DBR contents 0 No inversion 1 Invert data breakpoint comparators 4 2 L1EA Enable Level 1 Address Breakpoint Setting an L1EA bit enables the corresponding address breakpoint Clearing all three bits disables the address breakpoint 1 L1EPC Enable Level 1 PC breakpoint 0 Disabl...

Page 860: ...cess Supervisor write only BDM write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Address V Reset 0 0 0 Figure 34 8 PC Breakpoint Register n PBRn Table 34 12 PBRn Field Descriptions Field Description 31 1 Address PC Breakpoint Address The 31 bit address to be compared with the PC as a breakpoint trigger 0 V Valid Bit This bit must be set for the PC...

Page 861: ...te BDM read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBR3AC PBR2AC PBR1AC PBR0AC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 10 PC Breakpoint ASID Control Register PBAC Table 34 14 PBAC Field Descriptions Field Description 31 16 Reserved must be cleared 15 12 PBR3AC 11 8 PBR2A...

Page 862: ... 4 3 2 1 0 R W Address Reset Figure 34 11 Address Breakpoint Registers ABLR ABHR ABLR1 ABHR1 Table 34 15 ABLR and ABLR1 Field Description Field Description 31 0 Address Low Address Holds the 32 bit address marking the lower bound of the address breakpoint range Breakpoints for specific single addresses are programmed into ABLR or ABLR1 Table 34 16 ABHR and ABHR1 Field Description Field Description...

Page 863: ...eakpoint register as described in Table 34 20 which allows each PC breakpoint register to be associated with a unique virtual address and process DRc 4 0 0x0F DBMR 0x1F DBMR1 Access Supervisor write only BDM write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Mask Reset Figure 34 13 Data Breakpoint Mask Registers DBMR DBMR1 Table 34 18 DBMR DBMR1 Fi...

Page 864: ...TDR 29 13 before defining triggers A write to XTDR clears the CSR trigger status bits CSR BSTAT XTDR is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the WDMREG command Section 34 3 11 1 Resulting Set of Possible Trigger Combinations describes how to handle multiple breakpoint conditions DRc 4 0 0x14 PBASID Access Supervisor read write BDM read write 31 ...

Page 865: ...oint triggers 28 22 L2ED Enable level 2 data breakpoint Setting an L2ED bit enables the corresponding data breakpoint condition based on the size and placement on the processor s local data bus Clearing all ED bits disables data breakpoints 21 L2DI Level 2 data breakpoint invert Inverts the logical sense of all the data breakpoint comparators This can develop a trigger based on the occurrence of a...

Page 866: ...data breakpoint comparators This can develop a trigger based on the occurrence of a data value other than the DBR contents 0 No inversion 1 Invert data breakpoint comparators Table 34 21 XTDR Field Descriptions continued Field Description TDR Bit Description 20 Address breakpoint inverted Breakpoint is based outside the range between ABLR1 and ABHR1 19 Address breakpoint range The breakpoint is ba...

Page 867: ...C_breakpoint then if Address_breakpoint Data_breakpoint Address1_breakpoint Data1_breakpoint if PC_breakpoint then if Address1_breakpoint Data1_breakpoint if Address_breakpoint Data_breakpoint then if Address1_breakpoint Data1_breakpoint if Address1_breakpoint Data1_breakpoint then if Address_breakpoint Data_breakpoint if Address_breakpoint Data_breakpoint 4 2 L1EA Enable level 1 address breakpoin...

Page 868: ... dedicated hardware module Communication with the development system is managed through a dedicated high speed serial command interface Although some BDM operations such as CPU register accesses require the CPU to be halted other BDM commands such as memory accesses can be executed while the processor is running BDM is useful because In circuit emulation is not needed so physical and electrical ch...

Page 869: ...outputs While the processor is in this state all resources accessible through the debug module can be referenced This is the only chance to force the processor into emulation mode through CSR EMU After system initialization the processor s response to the GO command depends on the set of BDM commands performed while it is halted for a breakpoint Specifically if the PC register was loaded the GO co...

Page 870: ... 2 The development system serves as the serial communication channel master and must generate DSCLK The serial channel operates at a frequency from DC to 1 5 of the PSTCLK frequency The channel uses full duplex mode where data is sent and received simultaneously by master and slave devices The transmission consists of 17 bit packets composed of a status control bit and a 16 bit data word As shown ...

Page 871: ...r clock periods 34 4 1 3 Receive Packet Format The basic receive packet consists of 16 data bits and 1 status bit 34 4 1 3 1 Transmit Packet Format The basic transmit packet consists of 16 data bits and 1 reserved bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S Data Figure 34 17 Receive BDM Packet Table 34 22 Receive BDM Packet Field Description Field Description 16 S Status Indicates the status of...

Page 872: ...r Extension Word s Figure 34 19 BDM Command Format Table 34 24 BDM Field Descriptions Field Description 15 10 Operation Specifies the command These values are listed in Table 34 25 9 Reserved must be cleared 8 R W Direction of operand transfer 0 Data is written to the CPU or to memory from the development system 1 The transfer is from the CPU to the development system 7 6 Op Size Operand Data Size...

Page 873: ...tom half indicates the debug module s response to the previous development system commands Command and result transactions overlap to minimize latency Figure 34 20 Command Sequence Diagram 3 A D Address Data Determines whether the register field specifies a data or address register 0 Data register 1 Address register 2 0 Register Contains the register number in commands that operate on processor re...

Page 874: ...s the low order 16 address bits The debug module always returns a not ready response At the completion of cycle 3 the debug module initiates a memory read operation Any serial transfers that begin during a memory access return a not ready response Results are returned in the two serial transfer cycles after the memory access completes For any command performing a byte sized memory read operation t...

Page 875: ...y block DUMP Used with READ to dump large blocks of memory An initial READ executes to set up the starting address of the block and to retrieve the first result A DUMP command retrieves subsequent operands Steal 34 4 1 5 5 34 38 0x1D00 byte 0x1D40 word 0x1D80 lword Fill memory block FILL Used with WRITE to fill large blocks of memory An initial WRITE executes to set up the starting address of the ...

Page 876: ... Sequence Figure 34 22 RAREG RDREG Command Sequence Operand Data None Result Data The contents of the selected register are returned as a longword value most significant word first 34 4 1 5 2 Write A D Register WAREG WDREG The operand longword data is written to the specified address or data register A write alters all 32 register bits A bus error response is returned if the CPU core is not halted...

Page 877: ...d address Address space is defined by BAAR TT TM Hardware forces low order address bits to 0s for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned Command Result Formats 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0x1 0x9 0x0 0x0 A 31 16 A 15 0 Result X X X X X X X X D 7 0 Word Command 0x1 0x9 0x4 0x0 A 31 16 A 15 0 Result...

Page 878: ...34 4 1 5 4 Write Memory Location WRITE Write data to the memory location specified by the longword address BAAR TT TM defines address space Hardware forces low order address bits to 0s for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned XXX NOT READY READ LONG MS ADDR NOT READY LS ADDR NOT READY NEXT CMD NOT READY NEXT CMD LS RE...

Page 879: ... Command Formats 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte 0x1 0x8 0x0 0x0 A 31 16 A 15 0 X X X X X X X X D 7 0 Word 0x1 0x8 0x4 0x0 A 31 16 A 15 0 D 15 0 Longword 0x1 0x8 0x8 0x0 A 31 16 A 15 0 D 31 16 D 15 0 Figure 34 27 WRITE Command Format ...

Page 880: ...memory An initial READ is executed to set up the starting address of the block and to retrieve the first result If an initial READ is not executed before the first DUMP an illegal command response is returned The DUMP command retrieves subsequent operands The initial address increments by the operand size 1 2 or 4 and saves in a temporary register Subsequent DUMP commands use this address perform ...

Page 881: ...ally altered Command Result Formats Command Sequence Figure 34 30 DUMP Command Sequence Operand Data None 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0x1 0xD 0x0 0x0 Result X X X X X X X X D 7 0 Word Command 0x1 0xD 0x4 0x0 Result D 15 0 Longword Command 0x1 0xD 0x8 0x0 Result D 31 16 D 15 0 Figure 34 29 DUMP Command Result Formats XXX NOT READY DUMP B W XXX ILLEGAL NEXT CMD NOT READY NEXT ...

Page 882: ...he memory write Subsequent FILL commands use this address perform the write increment it by the current operand size and store the updated address in the temporary register If an initial WRITE is not executed preceding the first FILL command the illegal command response is returned NOTE The FILL command does not check for a valid address FILL is a valid command only when preceded by another FILL a...

Page 883: ...mes Prefetching begins at the current address in the PC and at the current privilege level If any register such as the PC or SR is altered by a BDM command while the processor is halted the updated value is used when prefetching resumes If a GO command issues and the CPU is not halted the command is ignored Command Sequence Figure 34 34 GO Command Sequence 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0...

Page 884: ... processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of the CSR BTB bits The specific sequence of PSTDDATA values is defined below 1 Debug signals a SYNC_PC command is pending 2 CPU completes the current instruction 3 CPU forces an instruction fetch to the next PC generates a PST equaling 0x5 value indicating a taken branch and...

Page 885: ... condition Bus hang caused by processor or external or internal alternate master Assert the breakpoint input to force a processor core halt If the bus hang was caused by a processor access send in FORCE_TA commands until the processor is halted as signaled by PST 0xF Due to pipeline and store buffer depths many memory accesses may be queued up behind the access causing the bus hang Repeated FORCE_...

Page 886: ...and return the 32 bit result Accesses to the processor memory control registers are always 32 bits wide regardless of register width The second and third words of the command form a 32 bit address which the debug module uses to generate a special bus cycle to access the specified control register The 12 bit Rc field is the same the processor s MOVEC instruction uses Command Result Formats 15 14 13...

Page 887: ...s Control Register ACR1 0x006 Access Control Register ACR2 0x007 Access Control Register ACR3 0x008 MMU Base Address Register MMUBAR 0x009 RGPIO Base Address Register RGPIOBAR 1 0x 0 1 80 0x 0 1 87 Data Registers 0 7 0 load 1 store 0x 0 1 88 0x 0 1 8F Address Registers 0 7 0 load 1 store A7 is user stack pointer 0x800 Other Stack Pointer OTHER_A7 0x801 Vector Base Register VBR 0x804 MAC Status Reg...

Page 888: ...e SR S bit 34 4 1 5 13 BDM Accesses of the EMAC Registers The presence of rounding logic in the output datapath of the EMAC requires special care for BDM initiated reads and writes of its programming model In particular any result rounding modes must be disabled during the read write process so the exact bit wise EMAC register contents are accessed For example a BDM read of an accumulator ACCx mus...

Page 889: ...ing and for additional notes on writes to the A7 stack pointers and the EMAC programming model Command Result Formats Command Sequence Figure 34 44 WCREG Command Sequence Operand Data This instruction requires two longword operands The first selects the register to the operand data writes to the second contains the data Result Data Successful write operations return 0xFFFF Bus errors on the write ...

Page 890: ...The data is returned most significant word first 34 4 1 5 16 Write Debug Module Register WDMREG The operand longword data is written to the specified debug module register All 32 bits of the register are altered by the write DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Command 0x...

Page 891: ...perand address range and data with mask These breakpoints can be configured into one or two level triggers with the exact trigger response also programmable The debug module programming model can be written from the external development system using the debug serial interface or from the processor s supervisor programming model using the WDEBUG instruction Only CSR is readable using the external d...

Page 892: ... the processor reaches a sample point which occurs once per instruction Again the hardware forces the PC breakpoint to occur before the targeted instruction executes and is precise This is possible because the PC breakpoint is enabled when interrupt sampling occurs For address and data breakpoints reporting is considered imprecise because several instructions may execute after the triggering addre...

Page 893: ...xception handler 4 It executes an RTE instruction when the exception handler finishes During the processing of the RTE FS is reloaded from the system stack If this bit field is set to 0010 the processor sets the emulator mode state and resumes execution of the original debug interrupt service routine This is signaled externally by the generation of the PST value that originally identified the debu...

Page 894: ... 4 3 Concurrent BDM and Processor Operation The debug module supports concurrent operation of the processor and most BDM commands BDM commands may be executed while the processor is running except these following operations that access processor memory registers Read write address and data registers Read write control registers For BDM commands that access memory the debug module requests the proc...

Page 895: ...ration The core stalls until two FIFO entries are available Table 34 30 shows the encoding of these signals Table 34 30 Processor Status Encoding PST 3 0 Definition 0x0 Continue execution Many instructions execute in one processor cycle If an instruction requires more clock cycles subsequent clock cycles are indicated by driving PSTDDATA outputs with this encoding 0x1 Begin execution of one instru...

Page 896: ...on 34 4 4 1 Begin Execution of Taken Branch PST 0x5 Also indicates that the SYNC_PC command has been issued 0x6 Begin execution of instruction plus a taken branch The processor completes execution of a taken conditional branch instruction and simultaneously starts executing the target instruction This is achieved through branch folding 0x7 Begin execution of return from exception RTE instruction 0...

Page 897: ...er the JMP instruction continues with the next instruction 34 4 4 2 Processor Stopped or Breakpoint State Change PST 0xE The 0xE encoding is generated either as a one or multiple cycle issue as follows When the core is stopped by a STOP instruction this encoding appears in multiple cycle format The ColdFire processor remains stopped until an interrupt occurs thus PSTDDATA outputs display 0xE until...

Page 898: ...ata 0xFFFF_FFFF The B marker occurs on the most significant nibble of PSTDDATA with the data of 0xFF following PSTDDATA 7 0 0xBF 0xFF 0xFF 0xFF 0xFX X indicates that the next PST value is guaranteed to not be 0xF The B marker occurs on the least significant nibble of PSTDDATA with the data of 0xFF following PSTDDATA 7 0 0xYB 0xFF 0xFF 0xFF 0xFF 0xXY X indicates the PST value is guaranteed not to b...

Page 899: ...he PSTDDATA output 2 3 or 4 bytes using a PST value of 0x9 0xA or 0xB Addresses use the markers x0D x0E or 0xF to store 2 3 or 4 bytes of address packets with address shifted right by 1 bit 34 4 5 1 User Instruction Set Table 34 32 shows the PSTDDATA specification for user mode instructions Rn represents any Dn An register In this definition the y suffix generally denotes the source and x denotes ...

Page 900: ...DDATA 0x1 0xB destination operand clr w ea x PSTDDATA 0x1 0x9 destination operand cmp b ea y Dx PSTDDATA 0x1 0x8 source operand cmp l ea y Dx PSTDDATA 0x1 0xB source operand cmp w ea y Dx PSTDDATA 0x1 0x9 source operand cmpa l ea y Ax PSTDDATA 0x1 0xB source operand cmpa w ea y Ax PSTDDATA 0x1 0x9 source operand cmpi b data Dx PSTDDATA 0x1 cmpi l data Dx PSTDDATA 0x1 cmpi w data Dx PSTDDATA 0x1 di...

Page 901: ...ce movem l list ea x PSTDDATA 0x1 0xB destination 3 movem l ea y list PSTDDATA 0x1 0xB source 3 moveq l data Dx PSTDDATA 0x1 muls l ea y Dx PSTDDATA 0x1 0xB source operand muls w ea y Dx PSTDDATA 0x1 0x9 source operand mulu l ea y Dx PSTDDATA 0x1 0xB source operand mulu w ea y Dx PSTDDATA 0x1 0x9 source operand mvs b ea y Dx PSTDDATA 0x1 0x8 source operand mvs w ea y Dx PSTDDATA 0x1 0x9 source ope...

Page 902: ...rce 0xB destination subx l Dy Dx PSTDDATA 0x1 swap w Dx PSTDDATA 0x1 tas b ea x PSTDDATA 0x1 0x8 source 0x8 destination tpf PST 0x1 tpf l data PST 0x1 tpf w data PST 0x1 trap data PSTDDATA 0x11 tst b ea x PSTDDATA 0x1 0x8 source operand tst l ea y PSTDDATA 0x1 0xB source operand tst w ea y PSTDDATA 0x1 0x9 source operand unlk Ax PSTDDATA 0x1 0xB destination operand wddata b ea y PSTDDATA 0x4 0x8 s...

Page 903: ...ion address is displayed only for those effective address fields defining variant addressing modes This includes the following ea x values An d16 An d8 An Xi d8 PC Xi 3 For move multiple instructions MOVEM the processor automatically generates line sized transfers if the operand address reaches a 0 modulo 16 boundary and there are four or more registers to be transferred For these line sized trans...

Page 904: ...s in the given mode move l MASK Rx PSTDDATA 0x1 msac l Ry Rx ACCx PSTDDATA 0x1 msac l Ry Rx ea y Rw ACCx PSTDDATA 0x1 0xB source operand msac w Ry Rx ACCx PSTDDATA 0x1 msac w Ry Rx ea y Rw ACCx PSTDDATA 0x1 0xB source operand Table 34 34 PSTDDATA Specification for Supervisor Mode Instructions Instruction Operand Syntax PSTDDATA Nibble cpushl dc Ax ic Ax bc Ax PSTDDATA 0x1 halt PSTDDATA 0x1 PSTDDAT...

Page 905: ...50 Recommended BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Developer reserved1 GND GND RESET EVDD2 GND Freescale reserved GND IVDD BKPT DSCLK Developer reserved1 DSI DSO GND Freescale reserved PSTCLK 2 Supplied by target 1 Pins reserved for BDM developer use TA PSTDDATA7 PSTDDATA5 PSTDDATA3 PSTDDATA1 PSTDDATA6 PSTDDATA4 PSTDDATA2 PSTDDATA0 ...

Page 906: ... chip control pins from the board edge connector through the standard four pin test access port TAP and the JTAG reset pin TRST 35 1 1 Block Diagram Figure 35 1 shows the block diagram of the JTAG module Figure 35 1 JTAG Block Diagram TDO DSO BKPT 5 bit TAP Instruction Register 4 0 1 bit Bypass Register 32 bit IDCODE Register TRST DSCLK TCLK TMS BKPT 0 31 TAP Controller TDI DSI 1 0 JTAG Module to ...

Page 907: ... for more information refer to Section 34 4 1 Background Debug Mode BDM JTAG_EN 0 35 2 External Signal Description The JTAG module has five input and one output external signals as described in Table 35 1 35 2 1 JTAG Enable JTAG_EN The JTAG_EN pin selects between the debug module and JTAG If JTAG_EN is low the debug module is selected if it is high the JTAG is selected Table 35 2 summarizes the pi...

Page 908: ...akpoint TMS BKPT The TMS pin is the test mode select input that sequences the TAP state machine TMS is sampled on the rising edge of TCLK The TMS pin has an internal pull up resistor The BKPT pin is used to request an external breakpoint Assertion of BKPT puts the processor into a halted state after the current instruction completes 35 2 4 Test Data Input Development Serial Input TDI DSI The TDI p...

Page 909: ...oller states The DSO pin provides serial output data in BDM mode 35 3 Memory Map Register Definition The JTAG module registers are not memory mapped and are only accessible through the TDO DSO pin 35 3 1 Instruction Shift Register IR The JTAG module uses a 5 bit shift register with no parity The IR transfers its value to a parallel hold register and applies an instruction on the falling edge of TC...

Page 910: ... the update DR state The DSE bit selects the drive strength used in JTAG mode IR 4 0 0_0001 IDCODE Access User read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PRN DC PIN JEDEC ID W Reset See note1 See note2 See note1 0 0 0 0 0 0 0 1 1 1 0 1 1 The reset values for PRN and PIN are device dependent 2 Varies depending on design center location Figure 3...

Page 911: ...module consists of a TAP controller state machine which is responsible for generating all control signals that execute the JTAG instructions and read write data registers 35 4 2 TAP Controller The TAP controller is a state machine that changes state based on the sequence of logical values on the TMS pin Figure 35 5 shows the machine s states The value shown next to each state is the value of the T...

Page 912: ...r for shift SAMPLE PRELOAD 00010 Selects boundary scan register for shifting sampling and preloading without disturbing functional operation SAMPLE 00011 Selects boundary scan register for shifting and sampling without disturbing functional operation RUN TEST IDLE TEST LOGIC RESET 1 1 SELECT DR SCAN CAPTURE DR EXIT1 DR PAUSE DR UPDATE DR SELECT IR SCAN SHIFT DR EXIT2 DR CAPTURE IR SHIFT IR EXIT1 I...

Page 913: ...n initialization data The update DR state and the falling edge of TCLK can then transfer this data to the update cells The data is applied to the external output pins by the EXTEST or CLAMP instruction 35 4 3 3 SAMPLE Instruction The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input pins and before the boundary scan cell at the output pins This sam...

Page 914: ...ircuit board testing HIGHZ turns off all output drivers including the 2 state drivers and selects the bypass register HIGHZ also asserts internal reset for the MCU system logic to force a predictable internal state 35 4 3 7 CLAMP Instruction The CLAMP instruction selects the 1 bit bypass register and asserts internal reset while simultaneously forcing all output pins and bidirectional pins configu...

Page 915: ...w power stop mode Leaving the test logic reset state negates the ability to achieve low power but does not otherwise affect device functionality The TCLK input is not blocked in low power stop mode To consume minimal power the TCLK input should be externally connected to EVDD The TMS TDI and TRST pins include on chip pull up resistors For minimal power consumption in low power stop mode these thre...

Page 916: ...imed out any write Changed core watchdog timer functional description section note from If the CWT is enabled then any write to If the CWT is enabled and has not timed out any write Added The SCMISR CFEI bit flags fault errors independent of the CFIER ECFEI setting Therefore if CFEI is set prior to setting ECFEI an interrupt is requested immediately after ECFEI is set to end of SCMISR section Adde...

Page 917: ...d Clock Recovery RCR Block section Updated SD_DQS signal descriptions USB OTG Changed ID reset value from 0x0041_FA05 to 0x0042_FA05 Corrected address offsets for the following registers CAPLENGTH from 0x0100 to 0x0103 HCIVERION from 0x0102 to 0x0100 DCIVERSION from 0x0120 to 0x0122 Corrected cross reference in USBCMD ATDTW field description Moved USBCMD ATDTW from bit location 12 to bit 14 Bit 12...

Page 918: ... PS field description DSPI Corrected first equation in Address Calculation for the First in and Last in Entries in the RX FIFO section from First in entry address TX FIFO base to First in entry address RX FIFO base UART Reworded note below UART block diagram Corrected note in UIPn CTS bit description from and value as UIPCRn RTS to and value as UIPCRn CTS Table A 2 Rev 3 to Rev 4 Changes Chapter D...

Page 919: ...es independently of the other bits Updated Load Mode Extended Mode Register Command lmr lemr section to clarify some of the information on the SDRAM mode registers and add a description of the mobile DDR extended mode register Edited Initialization Application Information section to create separate init sequence for each of the supported types of memory Added note to SDCFG1 RD_LAT field Note The r...

Page 920: ... and MCF54451 do not contain the PCI bus controller FlexBus Corrected timing diagrams for bursting in multiplexed AD mode The address on FB_AD does not increment only the starting address is available during the first bus cycle on FB_AD PCI Changed note at beginning of chapter that the MCF54450 and MCF54451 devices do not contain a PCI bus controller Table A 4 Rev 5 to Rev 6 Changes Chapter Descri...

Page 921: ...Revision History A 6 Freescale Semiconductor ...

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