Freescale Semiconductor MCF5329, Reference Manual, Page: 872 / 924

IEEE 1149.1 Test Access Port (JTAG)
37-6 Freescale Semiconductor
37.3.5 Boundary Scan Register
The boundary scan register is connected between TDI and TDO when the EXTEST or
SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on output pins,
and selects a logic value and direction for bidirectional pins or high impedance for tri-stated pins.
The boundary scan register contains bits for bonded-out and non bonded-out signals, excluding JTAG
signals, analog signals, power supplies, compliance enable pins, device configuration pins, and clock
signals.
37.4 Functional Description
37.4.1 JTAG Module
The JTAG module consists of a TAP controller state machine, which is responsible for generating all
control signals that execute the JTAG instructions and read/write data registers.
37.4.2 TAP Controller
The TAP controller is a state machine that changes state based on the sequence of logical values on the
TMS pin.
Figure 37-5 shows the machine’s states. The value shown next to each state is the value of the
TMS signal sampled on the rising edge of the TCLK signal.
Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state. As
Figure 37-5 shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also
causes the state machine to enter the test-logic-reset state, whatever the initial state.
IR[4:0]: 0_0110 Access: User
read-only
0
R DSE
W
Reset 0
Figure 37-4. 1-Bit TEST_CTRL Register
MCF5329 Reference Manual, Rev 3