Freescale Semiconductor MCF5329, Reference Manual, Page: 617 / 924

Synchronous Serial Interface (SSI)
Freescale Semiconductor 24-23
24.3.11 SSI Receive Configuration Register (SSI_RCR)
The SSI_RCR directs the receive operation of the SSI. A power-on reset clears all SSI_RCR bits.
However, an SSI reset does not affect the SSI_RCR bits.
Address: 0xFC0B_C020 (SSI_RCR) Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0
RX
EXT
RX
BIT0
RFEN1 RFEN0
0
RXDIR RSHFD RSCKP RFSI RFSL REFS
W
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Figure 24-18. SSI Receive Configuration Register (SSI_RCR)
Table 24-11. SSI_RCR Field Descriptions
Field Description
31–11 Reserved, must be cleared.
10
RXEXT
Receive data extension. Allows the SSI to store the received data word in sign-extended form. This bit affects data
storage only if the received data is lsb-aligned (RXBIT0 = 1)
0 Sign extension disabled
1 Sign extension enabled
9
RXBIT0
Receive bit 0 (Alignment). Allows SSI to receive the data word at bit position 0 or 15/31 in the receive shift register.
The shifting data direction can be msb or lsb first, controlled by the RSHFD bit.
0 msb aligned. Shifting with respect to bit 31 (if word length equals 16, 18, 20, 22 or 24) or bit 15 (if word length
equals 8, 10 or 12) of the receive shift register
1 lsb aligned. Shifting with respect to bit 0 of the receive shift register.
8
RFEN1
Receive FIFO enable 1.
• When the FIFO is enabled, the FIFO allows eight samples to be received by the SSI (per channel) (a ninth sample
can be shifting in) before the SSI_ISR[RDR1] bit is set.
• When the FIFO is disabled, SSI_ISR[RDR1] is set when a single sample is received by the SSI.
0 Receive FIFO 1 disabled
1 Receive FIFO 1 enabled
7
RFEN0
Receive FIFO enable 0. Similar description as RFEN1 but pertains to Rx FIFO 0.
0 Receive FIFO 0 disabled
1 Receive FIFO 0 enabled
6 Reserved, must be cleared.
5
RXDIR
Gated clock enable. In synchronous mode, this bit enables gated clock mode.
0 Gated clock mode disabled
1 Gated clock mode enabled
4
RSHFD
Receive shift direction. Controls whether the msb or lsb is received first in a sample.
0 Data received msb first
1 Data received lsb first
MCF5329 Reference Manual, Rev 3