Universal Serial Bus Interface – On-The-Go Module
Freescale Semiconductor
21-27
21.3.3.10 Master Interface Data Burst Size Register (BURSTSIZE)
This register is not defined in the EHCI specification. BURSTSIZE dynamically controls the burst size
during data movement on the initiator (master) interface.
21.3.3.11 Transmit FIFO Tuning Control Register (TXFILLTUNING)
This register is not defined in the EHCI specification. The TXFILLTUNING register controls performance
tuning associated with how the module posts data to the TX latency FIFO before moving the data onto the
USB bus. The specific areas of performance include how much data to post into the FIFO and an estimate
for how long that operation takes in the target system.
Definitions:
T
0
= Standard packet overhead
T
1
= Time to send data payload
T
s
= Total packet flight time (send-only) packet (
T
s
=
T
0
+
T
1
)
T
ff
= Time to fetch packet into TX FIFO up to specified level
T
p
= Total packet time (fetch and send) packet (
T
p
=
T
ff
+
T
s
)
Table 21-26. TTCTRL Field Descriptions
Field
Description
31
Reserved, must be cleared.
30–24
TTHA
TT Hub Address. This field is used to match against the Hub Address field in a QH or siTD to determine if the
packet is routed to the internal TT for directly attached FS/LS devices. If the hub address in the QH or siTD
does not match this address then the packet is broadcast on the high speed ports destined for a downstream
HS hub with the address in the QH or siTD.
23–0
Reserved, must be cleared.
Address: 0xFC0B_0160 (BURSTSIZE)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXPBURST
RXPBURST
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
Figure 21-24. Master Interface Data Burst Size (BURSTSIZE)
Table 21-27. BURSTSIZE Field Descriptions
Field
Description
31–16
Reserved, must be cleared.
15–8
TXPBURST
Programable TX burst length. Represents the maximum length of a burst in 32-bit words while moving data from
system memory to the USB bus. Must not be set to greater than 16.
7–0
RXPBURST
Programable RX burst length. This register represents the maximum length of a burst in 32-bit words while
moving data from the USB bus to system memory. Must not be set to greater than 16.
MCF5329 Reference Manual, Rev 3
Summary of Contents for MCF5329
Page 106: ...ColdFire Core 3 32 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 148: ...Cache 5 22 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 154: ...Static RAM SRAM 6 6 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 184: ...Power Management 8 18 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 204: ...Reset Controller Module 10 8 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 220: ...System Control Module SCM 11 16 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 228: ...Crossbar Switch XBS 12 8 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 268: ...General Purpose I O Module 13 40 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 392: ...SDRAM Controller SDRAMC 18 30 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 436: ...Fast Ethernet Controller FEC 19 44 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 594: ...FlexCAN 23 30 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 678: ...Pulse Width Modulation PWM Module 26 22 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 684: ...Watchdog Timer Module 27 6 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 704: ...DMA Timers DTIM0 DTIM3 29 12 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 754: ...UART Modules 31 34 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 770: ...I2 C Interface 32 16 Freescale Semiconductor MCF5329 Reference Manual Rev 3...
Page 866: ...Debug Module 36 50 Freescale Semiconductor MCF5329 Reference Manual Rev 3...