Freescale Semiconductor MCF5329, Reference Manual, Page: 149 / 924

Freescale Semiconductor 6-1
Chapter 6
Static RAM (SRAM)
6.1 Introduction
This chapter describes the on-chip static RAM (SRAM) implementation, including general operations,
configuration, and initialization. It also provides information and examples showing how to minimize
power consumption when using the SRAM.
6.1.1 Overview
The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a
single cycle. The location of the memory block can be specified to any 0-modulo-32K address within the
256-Mbyte address space (0x8000_0000 – 0x8FFF_FFFF). The memory is ideal for storing critical code
or data structures or for use as the system stack. Because the SRAM module is physically connected to the
processor's high-speed local bus, it can service processor-initiated accesses or memory-referencing
commands from the debug module.
Depending on configuration information, processor references may be sent to the cache and the SRAM
block simultaneously. If the reference maps into the region defined by the SRAM, the SRAM provides the
data back to the processor, and the cache data is discarded. Accesses from the SRAM module are not
cached.
The SRAM is dual-ported to provide access for any of the bus masters via the SRAM backdoor on the
crossbar switch. The SRAM is partitioned into two physical memory arrays to allow simultaneous access
to arrays by the processor core and another bus master. For more information on arbitration between
multiple masters accessing the SRAM, see
Chapter 11, “System Control Module (SCM) . ”
6.1.2 Features
The major features includes:
• One 32 Kbyte SRAM
• Single-cycle access
• Physically located on the processor's high-speed local bus
• Memory location programmable on any 0-modulo-32 Kbyte address
• Byte, word, and longword address capabilities
MCF5329 Reference Manual, Rev 3