Chapter 17 Gate Drive Unit (GDUV4)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
638
NOTE
The purpose of the GSUF flag is to allow dissipation of the energy in the
motor coils through the low side FETs in case of short reset pulses whilst
the motor is spinning.
17.3.2.8
GDU Clock Control Register 1 (GDUCLK1)
NOTE
The GBODC & GBOCD register bits must be set to the required value
before GBOE bit is set. If a different boost clock frequency and duty cycle
is required GBOE has to be cleared before new values to GBODC &
GBOCD are written.
1
GHHDIF
GDU High V
HD
Supply Interrupt Flag— The interrupt flag is set by hardware if GHHDF is set or if GHHDS is
cleared. If the GHHDIE bit is set an interrupt is requested. Writing a logic “1” to the bit field clears the flag.
0
GLVLSIF
GDU Low VLS Supply Interrupt Flag— The interrupt flag is set by hardware if GLVLSF is set or GLVLSS is
cleared. If the GLVLSIE bit is set an interrupt is requested.Writing a logic “1” to the bit field clears the flag.
Module Base + 0x0007
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime if GWP=0
7
6
5
4
3
2
1
0
R
0
GBOCD[4:0]
GBODC[1:0]
W
Reset
0
0
0
0
0
0
0
0
Figure 17-10. GDU Clock Control Register 1 (GDUCLK1)
Table 17-9. GDUCLK1 Register Field Descriptions
Field
Description
6-2
GBOCD[4:0]
GDU Boost Option Clock Divider — These bits select the clock divider factor which is used to divide down
the bus clock frequency f
BUS
for the boost converter clock f
BOOST
. These bits cannot be modified after GWP bit
is set. See
for divider factors. See also
Section 17.4.10, “Boost Converter
1-0
GBODC[1:0]
GDU Boost Option Clock Duty Cycle— These bits select the duty cycle of the boost option clock f
boost
. For
GBOCD[4]= 0 the duty cycle of the boost option clock is always 50%. These bits cannot be modified after GWP
bit is set.
00 Duty Cycle = 50%
01 Duty Cycle = 25%
10 Duty Cycle = 50%
11 Duty Cycle = 75%
Table 17-8. GDUF Register Field Descriptions
Field
Description
