Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Chapter 1 Device Overview MC9S12ZVM-Family
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor 63
insertion, going through the external FETs and back into the internal ADC measurements of external
voltages and currents.
Figure 1-8. Control Loop Delay Overview
The PWM deadtime (T
DEAD_X
) is an integral number of bus clock cycles, configured by the PMF
deadtime registers.
The GDU propagation delays (t
delon
, t
deloff
) are specified in the electrical parameter Table E-1 .
The FET turn on times (t
HGON
) are load dependent but are specified for particular loads in the electrical
parameter Table E-1 .
The current sense amplifier delay is highly dependent on external components.
The ADC delay until a result is available is specified as the conversion period N
CONV
in Table C-1 .
1.13.3.3 Static Timing Operation
The timing frame is static if it is the same in every control cycle (defined by reload frequency) and is
relative to start of the control cycle. The only settings modified from one control cycle to the next one are
the PWM duty cycle registers.
The main control cycle synchronization event is the PMF reload event. The PMF reload event can be
generated every n PWM periods.
This mode can optionally be extended by a timer channel trigger to PMF to change the PWM channel
operation (e.g. used for BLDCM commutation). In this case, the PMF configuration can propagate the
trigger through the control loop or can prevent propagation so the static timing of the control cycle and
inter-block coherency are not affected by the trigger.
At the end of the conversion sequence the first ADC command from the new sequence is loaded and the
ADC
x waits for the next trigger_x . The PTU continues to generate the trigger_x events for each trigger
time from the list until a new reload or async_reload occurs.
PWM with
PWM base
PWM cycle
deadtime
GDU
propagation
FET
turn on
Current sense
settling time
ADC delay
T
DEAD_x
t
delon
t
HGON
(tcslsst)