Chapter 2 Port Integration Module (S12ZVMPIMV1)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
109
2.3.4
PIM Generic Register Exceptions
This section lists registers with deviations from the generic description in one or more register bits.
2.3.4.1
Port P Polarity Select Register (PPSP)
2.3.4.2
Port P Interrupt Enable Register (PIEP)
Read: Anytime
1. Read: Always reads 0x00
Write: Unimplemented
Address 0x02F4 PPSP
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
0
0
0
0
0
PPSP2
PPS1P
PPSP0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-21. Port P Polarity Select Register
Table 2-19. Port P Polarity Select Register Field Descriptions
Field
Description
2-1
PPSP
See
Section 2.3.3.5, “Polarity Select Register
”
0
PPSP
Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
This bit also selects the polarity of the active interrupt edge.
This bit selects if a high or a low level on FAULT5 generates a fault event in PMF.
1 Pulldown device selected; rising edge selected; active-high level selected on FAULT5 input
0 Pullup device selected; falling edge selected; active-low level selected on FAULT5 input
Address 0x02F6 PIEP
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
OCIE1
0
0
0
0
PIEP2
PIEP1
PIEP0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-22. Port P Interrupt Enable Register
