Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 20 ECC Generation module (SRAM_ECCV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
682 Freescale Semiconductor
The single bit ECC errors generates an interrupt when enabled. The double bit ECC errors are reported by
the SRAM_ECC module, but are handled outside by MCU level. For more information see MMC
description.
20.3.1 Aligned 2 and 4 Byte Memory write access
During an aligned 2 or 4 byte memory write access no ECC check is performed. The internal ECC logic
generates the new ECC value based on the write data and writes the data words together with the generated
ECC values into the memory.
20.3.2 Other Memory write access
Other types of write accesses are separated into read-modify-write operation. During the first cycle, the
logic reads the data from the memory and performs an ECC check. If no ECC errors was detected then the
logic generates the new ECC value based on the read and write data and writes the new data word together
with the new ECC value into the memory. If required both 2 byte data words are updated.
If the module detects a single bit ECC error during the read cycle, then the logic generates the new ECC
value based on the corrected read and new write read. In the next cycle new data word and the new ECC
value are written into the memory. If required both 2 byte data words are updated. The SBEEIF bit is set.
Hence the single bit ECC error was corrected by the write access.
Figure 20-9 shows an example of a 2
byte non-aligned memory write access.
If the module detects a double bit ECC error during the read cycle, then the write access to the memory is
blocked and the initiator module is informed about the error.
1 or 3 byte write,
non-aligned 2
byte write
no 2
read data from the memory
old + new
data
-
write old + new data to the memory
single
bit
2
read data from the memory
cor
new data
SBEEIF
write cor new data to the
memory
double
bit
2
read data from the memory
unchanged
initiator module is
informed
ignore write data
read access
no 1 read from memory unchanged -
single
bit
1
(1)
read data from the memory
corrected
data
SBEEIF
write corrected data back to memory
double
bit
1
read from memory unchanged data mark as invalid
1. the next back to back read access to the memory will be delayed by one clock cycle
Table 20-9. Memory access cycles
Access type
ECC
error
access
cycle
Internal operation
Memory
content
Error indication