Chapter 19 Simple Sound Generator (SSGV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
668
Freescale Semiconductor
19.4
Functional Description
19.4.1
SSG Amplitude Generation
The SSG sound amplitude is presented as the duty cycle of PWM signal. The prescaler signal period is the
period of the PWM and the amplitude register SSGAMP contains the duty, the amplitude duty cycle is
SSGAMP/(SSGPS+1), when SSGAMP>=SSGPS+1, it will be 100%. SSGAMP has a buffer register, so
changing the SSGAMP will not disturb the amplitude PWM waveform before the synchronous reload
takes place.
Figure 19-21. SSG Amplitude Generation
Table 19-15. SSGDCNT Field Descriptions
Field
Description
7–0
DCNT[7:0]
SSG Tone Duration Counter bits —
The counter register is read only, It contains the tone cycle number. The counter will be reset to 0 when it reaches
the SSGDUR value. In any SSG stop case, the counter will also be reset to 0.
SSGAMP
SSGPS + 1
(x clock period)
(x clock period)
......
......
A-1
P-1 P
0
1
2
A-1
P
0 1
2
3
......
......
......
......
......
......
2
1
0
bus clock
RDR
amplitude PWM
A is value of SSGAMP buffer
where : RDR is the RDR bit of SSGCR
Pcounter is the prescaler counter
Pcounter
P is the value of SSGPS buffer
