Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 15 Liquid Crystal Display (LCD40F4BV3) Block Description
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
576 Freescale Semiconductor
Write: LCDEN anytime. To avoid segment flicker the clock prescaler bits, the bias select bit and the duty
select bits must not be changed when the LCD is enabled.
Table 15-4. LCDCR0 Field Descriptions
Field Description
7
LCDEN
LCD40F4BV3 Driver System Enable — The LCDEN bit starts the LCD waveform generator.
0 All frontplane and backplane pins are disabled. In addition, the LCD40F4BV3 system is disabled
and all LCD waveform generation clocks are stopped.
1 LCD driver system is enabled. All FP[39:0] pins with FP[39:0]EN set, will output an LCD driver
waveform The BP[3:0] pins will output an LCD40F4BV3 driver waveform based on the settings of DUTY0
and DUTY1.
4:3
LCLK[1:0]
LCD Clock Prescaler — The LCD clock prescaler bits determine the RTCCLK divider value to produce the LCD
clock frequency. For detailed description of the correlation between LCD clock prescaler bits and the divider
value please refer to
Table 15-8 .
2
BIAS
BIAS Voltage Level Select — This bit selects the bias voltage levels during various LCD operating modes, as
shown in Table 15-9 .
1:0
DUTY[1:0]
LCD Duty Select — The DUTY1 and DUTY0 bits select the duty (multiplex mode) of the LCD40F4BV3 driver
system, as shown in Table 15-9 .