Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
412
Freescale Semiconductor
10.8
Use Cases and Application Information
10.8.1
List Usage — CSL single buffer mode and RVL single buffer mode
In this use case both list types are configured for single buffer mode (CSL_BMOD=1’b0 and
RVL_BMOD=1’b0, CSL_SEL and RVL_SEL are forced to 1’b0). The index register for the CSL and RVL
are cleared to start from the top of the list with next conversion command and result storage in the
following cases:
•
The conversion flow reaches the command containing the “End-of-List” command type identifier
•
A Restart Request occurs at a sequence boundary
•
After an aborted conversion or conversion sequence
Figure 10-35. CSL Single Buffer Mode — RVL Single Buffer Mode Diagram
10.8.2
List Usage — CSL single buffer mode and RVL double buffer mode
In this use case the CSL is configured for single buffer mode (CSL_BMOD=1’b0) and the RVL is
configured for double buffer mode (RVL_BMOD=1’b1). In this buffer configuration only the result list
RVL is switched when the first conversion result of a CSL is stored after a CSL was successfully finished
or a CSL got aborted.
Figure 10-36. CSL Single Buffer Mode — RVL Single Buffer Mode Diagram
The last entirely filled RVL (an RVL where the corresponding CSL has been executed including the “End
Of List “ command type) is shown by register ADCEOLRI.
The CSL is used in single buffer mode and bit CSL_SEL is forced to 1’b0.
CSL_0
CSL_1
(unused)
RVL_0
RVL_1
(unused)
CSL_0
CSL_1
(unused)
RVL_0
RVL_1
