Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
355
10.2
Key Features
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Programmer’s Model with List Based Architecture for conversion command and result value
organization
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Selectable resolution of 8-bit, 10-bit, or 12-bit
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Channel select control for n external analog input channels
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Provides up to eight device internal channels (please see the device reference manual for
connectivity information and
•
Programmable sample time
•
A sample buffer amplifier for channel sampling (improved performance in view to influence of
channel input path resistance versus conversion accuracy)
•
Left/right justified result data
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Individual selectable VRH_0/1 and VRL_0/1 inputs on a conversion command basis (please see
)
•
Special conversions for selected VRH_0/1, VRL_0/1, (VRL_0/1 + VRH_0/1) / 2
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15 conversion interrupts with flexible interrupt organization per conversion result
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One dedicated interrupt for “End Of List” type commands
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Command Sequence List (CSL) with a maximum number of 64 command entries
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Provides conversion sequence abort
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Restart from top of active Command Sequence List (CSL)
•
The Command Sequence List and Result Value List are implemented in double buffered manner
(two lists in parallel for each function)
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Conversion Command (CSL) loading possible from System RAM or NVM
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Single conversion flow control register with software selectable access path
•
Two conversion flow control modes optimized to different application use cases
