Chapter 8 Timer Module (TIM16B8CV3) Block Description
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
299
Figure 8-4. Channel 7 Output Compare/Pulse Accumulator Logic
8.2
External Signal Description
The TIM16B8CV3 module has a selected number of external pins. Refer to device specification for exact
number.
8.2.1
IOC7 — Input Capture and Output Compare Channel 7
This pin serves as input capture or output compare for channel 7 . This can also be configured as pulse
accumulator input.
8.2.2
IOC6 - IOC0 — Input Capture and Output Compare Channel 6-0
Those pins serve as input capture or output compare for TIM16B8CV3 channel .
NOTE
For the description of interrupts see
.
8.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
8.3.1
Module Memory Map
The memory map for the TIM16B8CV3 module is given below in
. The address listed for each
register is the address offset. The total address for each register is the sum of the base address for the
TIM16B8CV3 module and the address offset for each register.
PULSE
ACCUMULATOR
PAD
TEN
CHANNEL 7 OUTPUT COMPARE
OCPD
TIOS7
