Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
232
Freescale
Semiconductor
7.1.2
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12CPMU_UHV_V5.
7.1.2.1
Run Mode
The voltage regulator is in Full Performance Mode (FPM).
NOTE
The voltage regulator is active, providing the nominal supply voltages with
full current sourcing capability (see also Appendix for VREG electrical
parameters). The features ACLK clock source, Low Voltage Interrupt (LVI),
Low Voltage Reset (LVR) and Power-On Reset (POR) are available.
The Phase Locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
The API is available.
•
PLL Engaged Internal (PEI)
— This is the default mode after System Reset and Power-On Reset.
— The Bus Clock is based on the PLLCLK.
— After reset the PLL is configured for 50MHz VCOCLK operation.
Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 12.5MHz and Bus Clock is
6.25MHz.
The PLL can be re-configured for other bus frequencies.
— The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M.
•
PLL Engaged External (PEE)
— The Bus Clock is based on the PLLCLK.
— This mode can be entered from default mode PEI by performing the following steps:
– Configure the PLL for desired bus frequency.
– Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if
necessary.
– Enable the external oscillator (OSCE bit).
– Wait for oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1).
•
PLL Bypassed External (PBE)
— The Bus Clock is based on the Oscillator Clock (OSCCLK).
— The PLLCLK is always on to qualify the external oscillator clock. Therefore it is necessary to
make sure a valid PLL configuration is used for the selected oscillator frequency.
— This mode can be entered from default mode PEI by performing the following steps:
– Make sure the PLL configuration is valid for the selected oscillator frequency.