Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
220
Freescale Semiconductor
in bytes[6:4], the other payload bytes may be compressed or complete addresses as indicated by the info
byte bits.
If the info bit for byte3 indicates a full CPU PC address, whereby bytes[5:3] are used, then the info bit
mapped to byte[4] is redundant and the byte[6] is unused because a line overflow has occurred. Similarly
a base address stored in bytes[4:2] causes line overflow, so bytes[6:5] are unused.
CXINF[6:4] indicate how many bytes in a line contain valid data, since tracing may terminate before a
complete line has been filled.
CXINF Information Byte Source Tracing
Pure PC mode tracing does not support timestamps or external event entries.
6.4.5.3
Timestamp
When set, the STAMP bit in DBGTCRL configures the DBG to add a timestamp to trace buffer entries in
Normal, Loop1 and Detail trace buffer modes. The timestamp is generated from a 16-bit counter and is
stored to the trace buffer line each time a trace buffer entry is made.
Table 6-56. Pure PC Mode Trace Buffer Format Single Source
Mode
8-Byte Wide Trace Buffer Line
7
6
5
4
3
2
1
0
CPU
CXINF
BASE
BASE
BASE
PLB3
PLB2
PLB1
PLB0
7
6
5
4
3
2
1
0
CXINF
MAT
PLEC
NB3
NB2
NB1
NB0
Figure 6-29. Pure PC Mode CXINF
Table 6-57. CXINF Field Descriptions
Field
Description
MAT
Mid Aligned Trigger
— This bit indicates a mid aligned trigger position. When a mid aligned trigger occurs, the
next trace buffer entry is a base address and the counter is incremented to a new line, independent of the number
of bytes used on the current line. The MAT bit is set on the current line, to indicate the position of the trigger.
When configured for begin or end aligned trigger, this bit has no meaning.
NOTE: In the case when ARM and TRIG are simultaneously set together in the same cycle that a new PC value
is registered, then this PC is stored to the same trace buffer line and MAT set.
0 Line filled without mid aligned trigger occurrence
1 Line last entry is the last PC entry before a mid aligned trigger
PLEC[2:0]
Payload Entry Count
— This field indicates the number of valid bytes in the trace buffer line
Binary encoding is used to indicate up to 7 valid bytes.
NBx
Payload Compression Indicator
— This field indicates if the corresponding payload byte is the lowest byte of a
base PC entry
0 Corresponding payload byte is a not the lowest byte of a base PC entry
1 Corresponding payload byte is the lowest byte of a base PC entry