Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 185
6.3.2 Register Descriptions
This section consists of the DBG register descriptions in address order. When ARM is set in DBGC1, the
only bits in the DBG module registers that can be written are ARM, and TRIG
6.3.2.1 Debug Control Register 1 (DBGC1)
Read: Anytime
0x013B DBGCD3
R
Bit 7 6 5 4 3 2 1 Bit 0
W
0x013C DBGCDM0
R
Bit 31 30 29 28 27 26 25 Bit 24
W
0x013D DBGCDM1
R
Bit 23 22 21 20 19 18 17 Bit 16
W
0x013E DBGCDM2
R
Bit 15 14 13 12 11 10 9 Bit 8
W
0x013F DBGCDM3
R
Bit 7 6 5 4 3 2 1 Bit 0
W
0x0140 DBGDCTL
R 0 0
INST
0
RW RWE reserved COMPE
W
0x0141-
0x0144
Reserved
R 0 0 0 0 0 0 0 0
W
0x0145 DBGDAH
R
DBGDA[23:16]
W
0x0146 DBGDAM
R
DBGDA[15:8]
W
0x0147 DBGDAL
R
DBGDA[7:0]
W
0x0148-
0x017F
Reserved
R 0 0 0 0 0 0 0 0
W
Address: 0x0100
7 6 5 4 3 2 1 0
0x0100 ARM
0
reserved BDMBP BRKCPU reserved EEVE
TRIG
Reset 0 0 0 0 0 0 0 0
Figure 6-3. Debug Control Register (DBGC1)
Address Name Bit 7 6 5 4 3 2 1 Bit 0
Figure 6-2. Quick Reference to DBG Registers