Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
168 Freescale Semiconductor
5.4.5.1 BDC Access Of CPU Registers
The CRN field of the READ_Rn and WRITE_Rn commands contains a pointer to the CPU registers. The
mapping of CRN to CPU registers is shown in
Table 5-9 . Accesses to CPU registers are always 32-bits
wide, regardless of implemented register width. This means that the BDC data transmission for these
commands is 32-bits long. The valid bits of the transfer are listed in the Valid Data Bits column. The other
bits of the transmission are redundant.
Attempted accesses of CPU registers using a CRN of 0xD,0xE or 0xF is invalid, returning the value 0xEE
for each byte and setting the ILLACC bit.
5.4.5.2 BDC Access Of Device Memory Mapped Resources
The device memory map is accessed using READ_MEM, DUMP_MEM, WRITE_MEM, FILL_MEM
and READ_SAME, which support different access sizes, as explained in the command descriptions.
When an unimplemented command occurs during a DUMP_MEM, FILL_MEM or READ_SAME
sequence, then that sequence is ended.
Illegal read accesses return a value of 0xEE for each byte. After an illegal access FILL_MEM and
READ_SAME commands are not valid, and it is necessary to restart the internal access sequence with
READ_MEM or WRITE_MEM. An illegal access does not break a DUMP_MEM sequence. After read
accesses that cause the RDINV bit to be set, DUMP_MEM and READ_SAME commands are valid, it is
not necessary to restart the access sequence with a READ_MEM.
The hardware forces low-order address bits to zero for longword accesses to ensure these accesses are
realigned to 0-modulo-size alignments.
Word accesses map to 2-bytes from within a 4-byte field as shown in Table 5-10 . Thus if address bits [1:0]
are both logic “1” the access is realigned so that it does not straddle the 4-byte boundary but accesses data
from within the addressed 4-byte field.
Table 5-9. CPU Register Number (CRN) Mapping
CPU Register Valid Data Bits Command Opcode Command Opcode
D0 [7:0] WRITE_D0 0x40 READ_D0 0x60
D1 [7:0] WRITE_D1 0x41 READ_D1 0x61
D2 [15:0] WRITE_D2 0x42 READ_D2 0x62
D3 [15:0] WRITE_D3 0x43 READ_D3 0x63
D4 [15:0] WRITE_D4 0x44 READ_D4 0x64
D5 [15:0] WRITE_D5 0x45 READ_D5 0x65
D6 [31:0] WRITE_D6 0x46 READ_D6 0x66
D7 [31:0] WRITE_D7 0x47 READ_D7 0x67
X [23:0] WRITE_X 0x48 READ_X 0x68
Y [23:0] WRITE_Y 0x49 READ_Y 0x69
SP [23:0] WRITE_SP 0x4A READ_SP 0x6A
PC [23:0] WRITE_PC 0x4B READ_PC 0x6B
CCR [15:0] WRITE_CCR 0x4C READ_CCR 0x6C