Freescale Semiconductor MC9S08PT60, Reference Manual

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((170 - 176) / 170) x 100 = 3.53%
For a 9-bit data and 2 stop bits character, data sampling of the stop bit takes the receiver
11 bit times x 16 RT 10 RT cycles = 186 RT cycles.
With the misaligned character shown in, the receiver counts 186 RT cycles at the point
when the count of the transmitting device is 12 bit times x 16 RT cycles = 192 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of
a fast 9-bit and 2 stop bits character with no errors is:
((186 - 192) / 186) x 100 = 3.23%
15.4.6 Additional SCI functions
The following sections describe additional SCI functions.
15.4.6.1 8- and 9-bit data modes
The SCI system, transmitter and receiver, can be configured to operate in 9-bit data mode
by setting SCI_C1[M]. In 9-bit mode, there is a ninth data bit to the left of the most
significant bit of the SCI data register. For the transmit data buffer, this bit is stored in T8
in SCI_C3. For the receiver, the ninth bit is held in SCI_C3[R8].
For coherent writes to the transmit data buffer, write to SCI_C3[T8] before writing to
SCI_D.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the
previous character, it is not necessary to write to SCI_C3[T8] again. When data is
transferred from the transmit data buffer to the transmit shifter, the value in SCI_C3[T8]
is copied at the same time data is transferred from SCI_D to the shifter.
The 9-bit data mode is typically used with parity to allow eight bits of data plus the parity
in the ninth bit, or it is used with address-mark wake-up so the ninth data bit can serve as
the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled
marker.
15.4.6.2 Stop mode operation
During all stop modes, clocks to the SCI module are halted.
No SCI module registers are affected in Stop3 mode.
Functional description
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
438 Freescale Semiconductor, Inc.