Freescale Semiconductor MC9S08PT60, Reference Manual

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• If the selected mode is output compare mode, then CnVH:L registers are updated
according to the SYNCEN bit. If (SYNCEN = 0), then CnVH:L registers are updated
after their second byte is written and on the next change of the FTM counter. If
(SYNCEN = 1), then CnVH:L registers are updated by PWM synchronization. See
CnVH:L registers synchronization .
• If the selected mode is not output compare mode and (SYNCEN = 1), then CnVH:L
registers are updated by PWM synchronization. See CnVH:L registers
synchronization .
12.4.11 PWM synchronization
PWM synchronization provides an opportunity to update registers with the contents of
their write buffers. It can also be used to synchronize two or more FlexTimer modules on
the same MCU.
PWM synchronization updates the MODH:L and CnVH:L registers with their write
buffers. It is also possible to force the FTM counter to its initial value and update the
CHnOM bits in OUTMASK using PWM synchronization.
Note
PWM synchronization is available only in combine mode.
12.4.11.1 Hardware trigger
Each hardware trigger is synchronized by the system clock. The input signals are:
trigger_0, trigger_1, and trigger_2.
A rising edge on the selected hardware trigger input (trigger n event) initiates PWM
synchronization. A hardware trigger is selected when its enable bit is set (TRIGn = 1
where n = 0, 1, or 2). The TRIGn bit is cleared when 0 is written to it or when the trigger
n event is detected.
For example, if TRIG0 and TRIG1 are enabled and only the trigger 1 event occurs, only
the TRIG1 bit is cleared.
If a trigger n event occurs together with a write to set the TRIGn bit, then the
synchronization is made, but the TRIGn bit remains set because of the last write.
Functional Description
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
360 Freescale Semiconductor, Inc.