Freescale Semiconductor HCS08 Series, Reference Manual

Page: 26 / 306

Chapter 2 Pins and Connections
MC9S08JS16 MCU Series Reference Manual, Rev. 4
26 Freescale Semiconductor
NOTE
Before the IRQ or RESET function is enabled, be sure to enable the GPIO
pullup in that function’s pin and wait about 2
μ
s. Otherwise the IRQ or
RESET configuration may fail.
2.3.5 Bootloader Mode Select (BLMS)
During a power-on-reset (POR), the CPU detects the state of the PTB3/BLMS pin that functions as a mode
select pin. When the logic is low and BKGD/MS is not pulled low, the CPU enters the bootloader mode.
During a power-on-reset (POR), an internal pullup device is automatically enabled in PTB3/BLMS pin.
Immediately after reset rises the pin functions as a general-purpose output only pin and an internal pullup
device is automatically disabled.
2.3.6 USB Data Pins (USBDP, USBDN)
The USBDP (D+) and USBDN (D–) pins are the analog input/output lines for full-speed data
communication in the USB physical layer (PHY) module. An optional internal pullup resistor for the
USBDP pin, R
PUDP
, is available.
2.3.7 General-Purpose I/O and Peripheral Ports
The MC9S08JS16 series of MCUs supports up to 14 general-purpose I/O pins, including two output-only
pins, which are shared with on-chip peripheral functions (timers, serial I/O, keyboard interrupts, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pullup device.
For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output .” For information about how and when on-chip peripheral systems use these pins, see the
appropriate module chapter.
Immediately after reset, all pins except the output-only pin (PTB2/BKGD/MS, PTB3/BLMS) are
configured as high-impedance general-purpose inputs with internal pullup devices disabled.
Table 2-1. Pin Availability by Package Pin-Count
Pin Number
(Package)
<-- Lowest Priority --> Highest
24 (QFN) 20 (SOIC) Port Pin Alt 1 Alt 2
1 4 PTB0 IRQ TCLK
2 5 PTB1 RESET
3 6 PTB2 BKGD MS
4 7 PTB3 BLMS